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809 lines
23 KiB
C++
809 lines
23 KiB
C++
/*******************************************************************************
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HARPtools by Chad D. Kersey, Summer 2011
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*******************************************************************************/
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#include <iostream>
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#include <iomanip>
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// #define USE_DEBUG 7
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// #define PRINT_ACTIVE_THREADS
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#include "include/types.h"
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#include "include/util.h"
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#include "include/archdef.h"
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#include "include/mem.h"
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#include "include/enc.h"
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#include "include/core.h"
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#include "include/debug.h"
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#ifdef EMU_INSTRUMENTATION
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#include "include/qsim-harp.h"
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#endif
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#define NO_MEM_READ 7
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#define LB_MEM_READ 0
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#define LH_MEM_READ 1
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#define LW_MEM_READ 2
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#define LBU_MEM_READ 4
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#define LHU_MEM_READ 5
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#define NO_MEM_WRITE 7
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#define SB_MEM_WRITE 0
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#define SH_MEM_WRITE 1
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#define SW_MEM_WRITE 2
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#define INIT_TRACE(trace_inst) \
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trace_inst.valid_inst = false; \
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trace_inst.pc = 0; \
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trace_inst.wid = schedule_w; \
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trace_inst.rs1 = -1; \
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trace_inst.rs2 = -1; \
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trace_inst.rd = -1; \
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trace_inst.vs1 = -1; \
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trace_inst.vs2 = -1; \
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trace_inst.vd = -1; \
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trace_inst.is_lw = false; \
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trace_inst.is_sw = false; \
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trace_inst.mem_addresses = new unsigned[a.getNThds()]; \
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for (int tid = 0; tid < a.getNThds(); tid++) trace_inst.mem_addresses[tid] = 0xdeadbeef; \
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trace_inst.mem_stall_cycles = 0; \
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trace_inst.fetch_stall_cycles = 0; \
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trace_inst.stall_warp = false; \
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trace_inst.wspawn = false; \
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trace_inst.stalled = false;
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#define CPY_TRACE(drain, source) \
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drain.valid_inst = source.valid_inst; \
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drain.pc = source.pc; \
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drain.wid = source.wid; \
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drain.rs1 = source.rs1; \
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drain.rs2 = source.rs2; \
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drain.rd = source.rd; \
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drain.vs1 = source.vs1; \
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drain.vs2 = source.vs2; \
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drain.vd = source.vd; \
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drain.is_lw = source.is_lw; \
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drain.is_sw = source.is_sw; \
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for (int tid = 0; tid < a.getNThds(); tid++) drain.mem_addresses[tid] = source.mem_addresses[tid]; \
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drain.mem_stall_cycles = source.mem_stall_cycles; \
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drain.fetch_stall_cycles = source.fetch_stall_cycles; \
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drain.stall_warp = source.stall_warp; \
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drain.wspawn = source.wspawn; \
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drain.stalled = false;
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using namespace Harp;
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using namespace std;
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void printTrace(trace_inst_t * trace, const char * stage_name)
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{
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cout << "********************************** " << stage_name << " *********************************\n";
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cout << "valid: " << trace->valid_inst << '\n';
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cout << "PC: " << hex << trace->pc << dec << '\n';
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cout << "wid: " << trace->wid << '\n';
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cout << "rd: " << trace->rd << "\trs1: " << trace->rs1 << "\trs2: " << trace->rs2 << '\n';
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cout << "is_lw: " << trace->is_lw << '\n';
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cout << "is_sw: " << trace->is_sw << '\n';
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cout << "fetch_stall_cycles: " << trace->fetch_stall_cycles << '\n';
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cout << "mem_stall_cycles: " << trace->mem_stall_cycles << '\n';
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cout << "stall_warp: " << trace->stall_warp << '\n';
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cout << "wspawn: " << trace->wspawn << '\n';
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cout << "stalled: " << trace->stalled << '\n';
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}
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#ifdef EMU_INSTRUMENTATION
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void Harp::reg_doRead(Word cpuId, Word regNum) {
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Harp::OSDomain::osDomain->do_reg(cpuId, regNum, 8, true);
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}
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void Harp::reg_doWrite(Word cpuId, Word regNum) {
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Harp::OSDomain::osDomain->do_reg(cpuId, regNum, 8, false);
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}
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#endif
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Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
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a(a), iDec(d), mem(mem), steps(4)
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{
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release_warp = false;
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foundSchedule = true;
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schedule_w = 0;
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INIT_TRACE(inst_in_fetch);
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INIT_TRACE(inst_in_decode);
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INIT_TRACE(inst_in_scheduler);
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INIT_TRACE(inst_in_exe);
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INIT_TRACE(inst_in_lsu);
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INIT_TRACE(inst_in_wb);
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for (int i = 0; i < 32; i++)
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{
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stallWarp[i] = false;
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for (int j = 0; j < 32; j++)
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{
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renameTable[i][j] = true;
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}
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}
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for(int i = 0; i < 32; i++)
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{
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vecRenameTable[i] = true;
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}
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cache_simulator = new Vcache_simX;
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m_trace = new VerilatedVcdC;
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cache_simulator->trace(m_trace, 99);
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m_trace->open("simXtrace.vcd");
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cache_simulator->reset = 1;
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cache_simulator->clk = 0;
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cache_simulator->eval();
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// m_trace->dump(10);
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cache_simulator->reset = 1;
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cache_simulator->clk = 1;
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cache_simulator->eval();
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// m_trace->dump(11);
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cache_simulator->reset = 0;
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cache_simulator->clk = 0;
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for (unsigned i = 0; i < a.getNWarps(); ++i)
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w.push_back(Warp(this, i));
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w[0].activeThreads = 1;
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w[0].spawned = true;
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}
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bool Core::interrupt(Word r0) {
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w[0].interrupt(r0);
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}
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void Core::step()
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{
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cout << "\n\n\n------------------------------------------------------\n";
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steps++;
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cout << "CYCLE: " << steps << '\n';
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cout << "Stalled Warps:\n";
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for (int widd = 0; widd < a.getNWarps(); widd++)
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{
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cout << stallWarp[widd] << " ";
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}
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cout << '\n';
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// cout << "Rename table\n";
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// for (int regii = 0; regii < 32; regii++)
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// {
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// cout << regii << ": " << renameTable[0][regii] << '\n';
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// }
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cout << '\n';
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this->writeback();
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this->load_store();
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this->execute_unit();
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this->scheduler();
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this->decode();
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this->fetch();
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if (release_warp)
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{
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release_warp = false;
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stallWarp[release_warp_num] = false;
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}
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}
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void Core::getCacheDelays(trace_inst_t * trace_inst)
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{
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static int curr_cycle = 0;
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if (trace_inst->valid_inst)
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{
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bool in_dcache_in_valid[a.getNThds()];
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unsigned in_dcache_in_address[a.getNThds()];
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unsigned in_dcache_mem_read;
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unsigned in_dcache_mem_write;
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if (trace_inst->is_lw)
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{
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in_dcache_mem_read = LW_MEM_READ;
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in_dcache_mem_write = NO_MEM_WRITE;
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}
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else if (trace_inst->is_sw)
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{
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in_dcache_mem_read = NO_MEM_READ;
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in_dcache_mem_write = SW_MEM_WRITE;
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}
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else
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{
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in_dcache_mem_read = NO_MEM_READ;
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in_dcache_mem_write = NO_MEM_WRITE;
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}
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for (int j = 0; j < a.getNThds(); j++)
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{
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if ((w[trace_inst->wid].tmask[j]) && (trace_inst->is_sw || trace_inst->is_lw))
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{
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in_dcache_in_valid[j] = true;
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in_dcache_in_address[j] = trace_inst->mem_addresses[j];
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}
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else
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{
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in_dcache_in_valid[j] = false;
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in_dcache_in_address[j] = 0xdeadbeef;
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}
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}
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cache_simulator->clk = 1;
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cache_simulator->eval();
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m_trace->dump(2*curr_cycle);
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cache_simulator->in_icache_pc_addr = trace_inst->pc;
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cache_simulator->in_icache_valid_pc_addr = 1;
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// DCache start
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cache_simulator->in_dcache_mem_read = in_dcache_mem_read;
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cache_simulator->in_dcache_mem_write = in_dcache_mem_write;
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for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
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{
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cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t];
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cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t];
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}
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// DCache end
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cache_simulator->clk = 0;
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cache_simulator->eval();
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m_trace->dump(2*curr_cycle+1);
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curr_cycle++;
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while((cache_simulator->out_icache_stall || cache_simulator->out_dcache_stall))
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{
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////////// Feed input
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if (cache_simulator->out_icache_stall)
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{
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cache_simulator->in_icache_pc_addr = trace_inst->pc;
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cache_simulator->in_icache_valid_pc_addr = 1;
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trace_inst->fetch_stall_cycles++;
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}
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else
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{
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cache_simulator->in_icache_valid_pc_addr = 0;
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}
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if (cache_simulator->out_dcache_stall)
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{
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cache_simulator->in_dcache_mem_read = in_dcache_mem_read;
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cache_simulator->in_dcache_mem_write = in_dcache_mem_write;
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for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
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{
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cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t];
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cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t];
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}
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trace_inst->mem_stall_cycles++;
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}
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else
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{
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cache_simulator->in_dcache_mem_read = NO_MEM_READ;
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cache_simulator->in_dcache_mem_write = NO_MEM_WRITE;
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for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
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{
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cache_simulator->in_dcache_in_valid[cur_t] = 0;
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}
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}
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cache_simulator->clk = 1;
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cache_simulator->eval();
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m_trace->dump(2*curr_cycle);
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//////// Feed input
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if (cache_simulator->out_icache_stall)
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{
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cache_simulator->in_icache_pc_addr = trace_inst->pc;
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cache_simulator->in_icache_valid_pc_addr = 1;
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}
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else
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{
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cache_simulator->in_icache_valid_pc_addr = 0;
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}
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if (cache_simulator->out_dcache_stall)
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{
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cache_simulator->in_dcache_mem_read = in_dcache_mem_read;
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cache_simulator->in_dcache_mem_write = in_dcache_mem_write;
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for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
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{
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cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t];
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cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t];
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}
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}
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else
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{
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cache_simulator->in_dcache_mem_read = NO_MEM_READ;
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cache_simulator->in_dcache_mem_write = NO_MEM_WRITE;
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for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
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{
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cache_simulator->in_dcache_in_valid[cur_t] = 0;
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}
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}
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cache_simulator->clk = 0;
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cache_simulator->eval();
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m_trace->dump(2*curr_cycle+1);
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curr_cycle++;
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}
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}
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}
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void Core::warpScheduler()
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{
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int numSteps = 0;
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bool cont;
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do
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{
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numSteps++;
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schedule_w = (schedule_w+1) % w.size();
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bool has_active_threads = (w[schedule_w].activeThreads > 0);
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bool stalled = stallWarp[schedule_w];
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cont = ((!has_active_threads) || (stalled)) && (numSteps <= w.size());
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// cout << "&&&&&&&WID: " << schedule_w << '\n';
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// cout << "activeThreads: " << w[schedule_w].activeThreads << "\t!has_active_threads: " << (!has_active_threads) << '\n';
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// cout << "stalled: " << stalled << '\n';
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// cout << "numSteps: " << numSteps << " CONT: " << cont << '\n';
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} while (cont);
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if (numSteps > w.size())
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{
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this->foundSchedule = false;
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}
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else
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{
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this->foundSchedule = true;
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}
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}
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void Core::fetch()
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{
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#ifdef PRINT_ACTIVE_THREADS
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cout << endl << "Threads:";
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#endif
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// D(-1, "Found schedule: " << foundSchedule);
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if ((!inst_in_scheduler.stalled) && (inst_in_fetch.fetch_stall_cycles == 0))
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{
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// CPY_TRACE(inst_in_decode, inst_in_fetch);
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// if (w[schedule_w].activeThreads)
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{
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INIT_TRACE(inst_in_fetch);
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if (foundSchedule)
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{
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D(3, "Core step stepping warp " << schedule_w << '[' << w[schedule_w].activeThreads << ']');
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w[schedule_w].step(&inst_in_fetch);
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D(3, "Now " << w[schedule_w].activeThreads << " active threads in " << schedule_w);
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this->getCacheDelays(&inst_in_fetch);
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if (inst_in_fetch.stall_warp)
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{
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stallWarp[inst_in_fetch.wid] = true;
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}
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}
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warpScheduler();
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}
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}
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else
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{
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inst_in_fetch.stalled = false;
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if (inst_in_fetch.fetch_stall_cycles > 0) inst_in_fetch.fetch_stall_cycles--;
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}
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printTrace(&inst_in_fetch, "Fetch");
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// #ifdef PRINT_ACTIVE_THREADS
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for (unsigned j = 0; j < w[schedule_w].tmask.size(); ++j) {
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if (w[schedule_w].activeThreads > j && w[schedule_w].tmask[j]) cout << " 1";
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else cout << " 0";
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if (j != w[schedule_w].tmask.size()-1 || schedule_w != w.size()-1) cout << ',';
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}
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// #endif
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#ifdef PRINT_ACTIVE_THREADS
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cout << endl;
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#endif
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}
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void Core::decode()
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{
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if ((inst_in_fetch.fetch_stall_cycles == 0) && !inst_in_scheduler.stalled)
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{
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CPY_TRACE(inst_in_decode, inst_in_fetch);
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INIT_TRACE(inst_in_fetch);
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}
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//printTrace(&inst_in_decode, "Decode");
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}
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void Core::scheduler()
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{
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if (!inst_in_scheduler.stalled)
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{
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CPY_TRACE(inst_in_scheduler, inst_in_decode);
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INIT_TRACE(inst_in_decode);
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}
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//printTrace(&inst_in_scheduler, "scheduler");
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}
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void Core::load_store()
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{
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bool do_nothing = false;
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if ((inst_in_lsu.mem_stall_cycles > 0) || (inst_in_lsu.stalled))
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{
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// LSU currently busy
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if ((inst_in_scheduler.is_lw || inst_in_scheduler.is_sw))
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{
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inst_in_scheduler.stalled = true;
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}
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do_nothing = true;
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}
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else
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{
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// LSU not busy
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if (inst_in_scheduler.is_lw || inst_in_scheduler.is_sw)
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{
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// Scheduler has LSU inst
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bool scheduler_srcs_ready = true;
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if (inst_in_scheduler.rs1 > 0)
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{
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scheduler_srcs_ready = scheduler_srcs_ready && renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs1];
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}
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if (inst_in_scheduler.rs2 > 0)
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{
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scheduler_srcs_ready = scheduler_srcs_ready && renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs2];
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}
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if(inst_in_scheduler.vs1 > 0)
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{
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scheduler_srcs_ready = scheduler_srcs_ready && vecRenameTable[inst_in_scheduler.vs1];
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}
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if(inst_in_scheduler.vs2 > 0)
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{
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scheduler_srcs_ready = scheduler_srcs_ready && vecRenameTable[inst_in_scheduler.vs2];
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}
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if (scheduler_srcs_ready)
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{
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if (inst_in_scheduler.rd != -1) renameTable[inst_in_scheduler.wid][inst_in_scheduler.rd] = false;
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if (inst_in_scheduler.rd != -1) vecRenameTable[inst_in_scheduler.vd] = false;
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CPY_TRACE(inst_in_lsu, inst_in_scheduler);
|
|
INIT_TRACE(inst_in_scheduler);
|
|
}
|
|
else
|
|
{
|
|
inst_in_scheduler.stalled = true;
|
|
// INIT_TRACE(inst_in_lsu);
|
|
do_nothing = true;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
// INIT_TRACE(inst_in_lsu);
|
|
do_nothing = true;
|
|
}
|
|
}
|
|
|
|
if (inst_in_lsu.mem_stall_cycles > 0) inst_in_lsu.mem_stall_cycles--;
|
|
|
|
//printTrace(&inst_in_lsu, "LSU");
|
|
}
|
|
|
|
void Core::execute_unit()
|
|
{
|
|
// cout << "$$$$$$$$$$$$$$$$$$$ EXE START\n";
|
|
bool do_nothing = false;
|
|
// EXEC is always not busy
|
|
if (inst_in_scheduler.is_lw || inst_in_scheduler.is_sw)
|
|
{
|
|
// Not an execute instruction
|
|
// INIT_TRACE(inst_in_exe);
|
|
do_nothing = true;
|
|
}
|
|
else
|
|
{
|
|
bool scheduler_srcs_ready = true;
|
|
if (inst_in_scheduler.rs1 > 0)
|
|
{
|
|
scheduler_srcs_ready = scheduler_srcs_ready && renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs1];
|
|
// cout << "Rename RS1: " << inst_in_scheduler.rs1 << " is " << renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs1] << " wid: " << inst_in_scheduler.wid << '\n';
|
|
}
|
|
|
|
if (inst_in_scheduler.rs2 > 0)
|
|
{
|
|
scheduler_srcs_ready = scheduler_srcs_ready && renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs2];
|
|
// cout << "Rename RS2: " << inst_in_scheduler.rs1 << " is " << renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs2] << " wid: " << inst_in_scheduler.wid << '\n';
|
|
}
|
|
|
|
if(inst_in_scheduler.vs1 > 0)
|
|
{
|
|
scheduler_srcs_ready = scheduler_srcs_ready && vecRenameTable[inst_in_scheduler.vs1];
|
|
}
|
|
if(inst_in_scheduler.vs2 > 0)
|
|
{
|
|
scheduler_srcs_ready = scheduler_srcs_ready && vecRenameTable[inst_in_scheduler.vs2];
|
|
}
|
|
|
|
if (scheduler_srcs_ready)
|
|
{
|
|
if (inst_in_scheduler.rd != -1) {
|
|
// cout << "rename setting rd: " << inst_in_scheduler.rd << " to not useabel wid: " << inst_in_scheduler.wid << '\n';
|
|
renameTable[inst_in_scheduler.wid][inst_in_scheduler.rd] = false;
|
|
}
|
|
if(inst_in_scheduler.vd != -1) {
|
|
vecRenameTable[inst_in_scheduler.vd] = false;
|
|
}
|
|
CPY_TRACE(inst_in_exe, inst_in_scheduler);
|
|
INIT_TRACE(inst_in_scheduler);
|
|
}
|
|
else
|
|
{
|
|
cout << "&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY\n";
|
|
inst_in_scheduler.stalled = true;
|
|
// INIT_TRACE(inst_in_exe);
|
|
do_nothing = true;
|
|
}
|
|
}
|
|
|
|
// if (!do_nothing)
|
|
// {
|
|
|
|
// }
|
|
|
|
//printTrace(&inst_in_exe, "execute_unit");
|
|
// INIT_TRACE(inst_in_exe);
|
|
}
|
|
|
|
void Core::writeback()
|
|
{
|
|
|
|
|
|
if (inst_in_wb.rd > 0) renameTable[inst_in_wb.wid][inst_in_wb.rd] = true;
|
|
if (inst_in_wb.vd > 0) vecRenameTable[inst_in_wb.vd] = true;
|
|
|
|
if (inst_in_wb.stall_warp)
|
|
{
|
|
stallWarp[inst_in_wb.wid] = false;
|
|
// release_warp = true;
|
|
// release_warp_num = inst_in_wb.wid;
|
|
}
|
|
|
|
|
|
INIT_TRACE(inst_in_wb);
|
|
|
|
bool serviced_exe = false;
|
|
bool serviced_mem = false;
|
|
if ((inst_in_exe.rd > 0) || (inst_in_exe.stall_warp))
|
|
{
|
|
CPY_TRACE(inst_in_wb, inst_in_exe);
|
|
INIT_TRACE(inst_in_exe);
|
|
|
|
serviced_exe = true;
|
|
// cout << "WRITEBACK SERVICED EXE\n";
|
|
}
|
|
|
|
if (inst_in_lsu.is_sw)
|
|
{
|
|
INIT_TRACE(inst_in_lsu);
|
|
}
|
|
else
|
|
{
|
|
if (((inst_in_lsu.rd > 0) || (inst_in_lsu.vd > 0)) && (inst_in_lsu.mem_stall_cycles == 0))
|
|
{
|
|
if (serviced_exe)
|
|
{
|
|
cout << "$$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used\n";
|
|
inst_in_lsu.stalled = true;
|
|
}
|
|
else
|
|
{
|
|
serviced_mem = true;
|
|
CPY_TRACE(inst_in_wb, inst_in_lsu);
|
|
INIT_TRACE(inst_in_lsu);
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
// if (!serviced_exe && !serviced_mem) INIT_TRACE(inst_in_wb);
|
|
|
|
//printTrace(&inst_in_wb, "Writeback");
|
|
|
|
}
|
|
|
|
|
|
bool Core::running() const {
|
|
bool stages_have_valid = inst_in_fetch.valid_inst || inst_in_decode.valid_inst || inst_in_scheduler.valid_inst ||
|
|
inst_in_lsu.valid_inst || inst_in_exe.valid_inst || inst_in_wb.valid_inst;
|
|
|
|
if (stages_have_valid) return true;
|
|
|
|
for (unsigned i = 0; i < w.size(); ++i)
|
|
if (w[i].running())
|
|
{
|
|
cout << "Warp ID " << i << " is running\n";
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void Core::printStats() const {
|
|
unsigned long insts = 0;
|
|
for (unsigned i = 0; i < w.size(); ++i)
|
|
insts += w[i].insts;
|
|
|
|
cerr << "Total steps: " << steps << endl;
|
|
for (unsigned i = 0; i < w.size(); ++i) {
|
|
cout << "=== Warp " << i << " ===" << endl;
|
|
w[i].printStats();
|
|
}
|
|
}
|
|
|
|
Warp::Warp(Core *c, Word id) :
|
|
core(c), pc(0x80000000), interruptEnable(true),
|
|
supervisorMode(true), activeThreads(0), reg(0), pred(0),
|
|
shadowReg(core->a.getNRegs()), shadowPReg(core->a.getNPRegs()), id(id),
|
|
spawned(false), steps(0), insts(0), loads(0), stores(0), VLEN(1024)
|
|
{
|
|
D(3, "Creating a new thread with PC: " << hex << this->pc << '\n');
|
|
/* Build the register file. */
|
|
Word regNum(0);
|
|
for (Word j = 0; j < core->a.getNThds(); ++j) {
|
|
reg.push_back(vector<Reg<Word> >(0));
|
|
for (Word i = 0; i < core->a.getNRegs(); ++i) {
|
|
reg[j].push_back(Reg<Word>(id, regNum++));
|
|
}
|
|
|
|
pred.push_back(vector<Reg<bool> >(0));
|
|
for (Word i = 0; i < core->a.getNPRegs(); ++i) {
|
|
pred[j].push_back(Reg<bool>(id, regNum++));
|
|
}
|
|
|
|
bool act = false;
|
|
if (j == 0) act = true;
|
|
tmask.push_back(act);
|
|
shadowTmask.push_back(act);
|
|
}
|
|
|
|
Word csrNum(0);
|
|
for (Word i = 0; i < (1<<12); i++)
|
|
{
|
|
csr.push_back(Reg<uint16_t>(id, regNum++));
|
|
}
|
|
|
|
/* Set initial register contents. */
|
|
reg[0][0] = (core->a.getNThds()<<(core->a.getWordSize()*8 / 2)) | id;
|
|
}
|
|
|
|
void Warp::step(trace_inst_t * trace_inst) {
|
|
Size fetchPos(0), decPos, wordSize(core->a.getWordSize());
|
|
vector<Byte> fetchBuffer(wordSize);
|
|
|
|
if (activeThreads == 0) return;
|
|
|
|
// ++steps;
|
|
|
|
D(3, "in step pc=0x" << hex << pc);
|
|
cout << "help: in PC: " << hex << pc << dec << '\n';
|
|
|
|
// std::cout << "pc: " << hex << pc << "\n";
|
|
|
|
trace_inst->pc = pc;
|
|
|
|
/* Fetch and decode. */
|
|
if (wordSize < sizeof(pc)) pc &= ((1ll<<(wordSize*8))-1);
|
|
Instruction *inst;
|
|
bool fetchMore;
|
|
|
|
fetchMore = false;
|
|
unsigned fetchSize(wordSize - (pc+fetchPos)%wordSize);
|
|
fetchBuffer.resize(fetchPos + fetchSize);
|
|
Word fetched = core->mem.fetch(pc + fetchPos, supervisorMode);
|
|
writeWord(fetchBuffer, fetchPos, fetchSize, fetched);
|
|
decPos = 0;
|
|
inst = core->iDec.decode(fetchBuffer, decPos, trace_inst);
|
|
|
|
D(3, "Fetched at 0x" << hex << pc);
|
|
D(3, "0x" << hex << pc << ": " << *inst);
|
|
|
|
// Update pc
|
|
pc += decPos;
|
|
|
|
// Execute
|
|
|
|
inst->executeOn(*this, trace_inst);
|
|
|
|
|
|
// At Debug Level 3, print debug info after each instruction.
|
|
// #ifdef USE_DEBUG
|
|
// if (USE_DEBUG >= 3) {
|
|
D(3, "Register state:");
|
|
for (unsigned i = 0; i < reg[0].size(); ++i) {
|
|
D_RAW(" %r" << setfill(' ') << setw(2) << dec << i << ':');
|
|
for (unsigned j = 0; j < (this->activeThreads); ++j)
|
|
D_RAW(' ' << setfill('0') << setw(8) << hex << reg[j][i] << setfill(' ') << ' ');
|
|
D_RAW('(' << shadowReg[i] << ')' << endl);
|
|
}
|
|
|
|
|
|
D(3, "Thread mask:");
|
|
D_RAW(" ");
|
|
for (unsigned i = 0; i < tmask.size(); ++i) D_RAW(tmask[i] << ' ');
|
|
D_RAW(endl);
|
|
D_RAW(endl);
|
|
D_RAW(endl);
|
|
// }
|
|
// #endif
|
|
|
|
// Clean up.
|
|
delete inst;
|
|
}
|
|
|
|
bool Warp::interrupt(Word r0) {
|
|
if (!interruptEnable) return false;
|
|
|
|
#ifdef EMU_INSTRUMENTATION
|
|
Harp::OSDomain::osDomain->do_int(0, r0);
|
|
#endif
|
|
|
|
shadowActiveThreads = activeThreads;
|
|
shadowTmask = tmask;
|
|
shadowInterruptEnable = interruptEnable; /* For traps. */
|
|
shadowSupervisorMode = supervisorMode;
|
|
|
|
for (Word i = 0; i < reg[0].size(); ++i) shadowReg[i] = reg[0][i];
|
|
for (Word i = 0; i < pred[0].size(); ++i) shadowPReg[i] = pred[0][i];
|
|
for (Word i = 0; i < reg.size(); ++i) tmask[i] = 1;
|
|
|
|
shadowPc = pc;
|
|
activeThreads = 1;
|
|
interruptEnable = false;
|
|
supervisorMode = true;
|
|
reg[0][0] = r0;
|
|
pc = core->interruptEntry;
|
|
|
|
return true;
|
|
}
|
|
|
|
void Warp::printStats() const {
|
|
cout << "Steps : " << steps << endl
|
|
<< "Insts : " << insts << endl
|
|
<< "Loads : " << loads << endl
|
|
<< "Stores: " << stores << endl;
|
|
|
|
unsigned const grade = reg[0][28];
|
|
|
|
if (grade == 1) cout << "GRADE: PASSED\n";
|
|
else cout << "GRADE: FAILED " << (grade >> 1) << "\n";
|
|
}
|