mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-25 06:17:38 -04:00
143 lines
No EOL
4.6 KiB
Bash
Executable file
143 lines
No EOL
4.6 KiB
Bash
Executable file
#!/bin/bash
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set -e
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make
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echo ./../tests/riscv/isa/rv32ui-p-add.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-add.hex
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echo ./../tests/riscv/isa/rv32ui-p-addi.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-addi.hex
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echo ./../tests/riscv/isa/rv32ui-p-and.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-and.hex
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echo ./../tests/riscv/isa/rv32ui-p-andi.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-andi.hex
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echo ./../tests/riscv/isa/rv32ui-p-auipc.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-auipc.hex
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echo ./../tests/riscv/isa/rv32ui-p-beq.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-beq.hex
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echo ./../tests/riscv/isa/rv32ui-p-bge.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bge.hex
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echo ./../tests/riscv/isa/rv32ui-p-bgeu.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bgeu.hex
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echo ./../tests/riscv/isa/rv32ui-p-blt.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-blt.hex
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echo ./../tests/riscv/isa/rv32ui-p-bltu.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bltu.hex
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echo ./../tests/riscv/isa/rv32ui-p-bne.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bne.hex
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echo ./../tests/riscv/isa/rv32ui-p-jal.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-jal.hex
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echo ./../tests/riscv/isa/rv32ui-p-jalr.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-jalr.hex
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echo ./../tests/riscv/isa/rv32ui-p-lb.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lb.hex
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echo ./../tests/riscv/isa/rv32ui-p-lbu.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lbu.hex
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echo ./../tests/riscv/isa/rv32ui-p-lh.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lh.hex
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echo ./../tests/riscv/isa/rv32ui-p-lhu.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lhu.hex
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echo ./../tests/riscv/isa/rv32ui-p-lui.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lui.hex
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echo ./../tests/riscv/isa/rv32ui-p-lw.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lw.hex
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echo ./../tests/riscv/isa/rv32ui-p-or.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-or.hex
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echo ./../tests/riscv/isa/rv32ui-p-ori.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-ori.hex
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echo ./../tests/riscv/isa/rv32ui-p-sb.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sb.hex
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echo ./../tests/riscv/isa/rv32ui-p-sh.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sh.hex
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echo ./../tests/riscv/isa/rv32ui-p-simple.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-simple.hex
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echo ./../tests/riscv/isa/rv32ui-p-sll.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sll.hex
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echo ./../tests/riscv/isa/rv32ui-p-slli.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-slli.hex
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echo ./../tests/riscv/isa/rv32ui-p-slt.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-slt.hex
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echo ./../tests/riscv/isa/rv32ui-p-slti.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-slti.hex
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echo ./../tests/riscv/isa/rv32ui-p-sltiu.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sltiu.hex
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echo ./../tests/riscv/isa/rv32ui-p-sltu.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sltu.hex
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echo ./../tests/riscv/isa/rv32ui-p-sra.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sra.hex
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echo ./../tests/riscv/isa/rv32ui-p-srai.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-srai.hex
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echo ./../tests/riscv/isa/rv32ui-p-srl.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-srl.hex
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echo ./../tests/riscv/isa/rv32ui-p-srli.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-srli.hex
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echo ./../tests/riscv/isa/rv32ui-p-sub.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sub.hex
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echo ./../tests/riscv/isa/rv32ui-p-sw.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sw.hex
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echo ./../tests/riscv/isa/rv32ui-p-xor.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-xor.hex
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echo ./../tests/riscv/isa/rv32ui-p-xori.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-xori.hex
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echo ./../tests/riscv/isa/rv32um-p-div.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-div.hex
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echo ./../tests/riscv/isa/rv32um-p-divu.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-divu.hex
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echo ./../tests/riscv/isa/rv32um-p-mul.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mul.hex
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echo ./../tests/riscv/isa/rv32um-p-mulh.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mulh.hex
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echo ./../tests/riscv/isa/rv32um-p-mulhsu.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mulhsu.hex
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echo ./../tests/riscv/isa/rv32um-p-mulhu.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mulhu.hex
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echo ./../tests/riscv/isa/rv32um-p-rem.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-rem.hex
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echo ./../tests/riscv/isa/rv32um-p-remu.hex
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./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-remu.hex |