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90 lines
1.6 KiB
C++
90 lines
1.6 KiB
C++
#pragma once
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#include "VVX_cache.h"
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#include "VVX_cache__Syms.h"
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#include "verilated.h"
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//#ifdef VCD_OUTPUT
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#include <verilated_vcd_c.h>
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//#endif
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//#include <VX_config.h>
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#include "ram.h"
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#include <ostream>
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#include <vector>
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#include <queue>
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#define ENABLE_DRAM_STALLS
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#define DRAM_LATENCY 100
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#define DRAM_RQ_SIZE 16
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#define DRAM_STALLS_MODULO 16
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#define GLOBAL_BLOCK_SIZE 16
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typedef struct {
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int cycles_left;
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uint8_t *data;
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unsigned tag;
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} dram_req_t;
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typedef struct {
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char valid;
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char rw;
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unsigned byteen;
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unsigned *addr;
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unsigned *data;
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unsigned int tag;
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} core_req_t;
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class CacheSim {
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public:
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CacheSim();
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virtual ~CacheSim();
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bool busy();
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void reset();
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void step();
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void wait(uint32_t cycles);
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void attach_ram(RAM* ram);
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void run(); //run until all reqs are empty
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void clear_req();
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void send_req(core_req_t *req);
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bool assert_equal(unsigned int* data, unsigned int tag);
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//void time_analyisis
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//display funcs
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void get_dram_req();
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void get_core_rsp(unsigned int (&rsp)[4]);
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void get_core_req();
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bool get_core_req_ready();
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bool get_core_rsp_ready();
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void get_dram_rsp();
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void display_hit_miss();
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private:
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void eval();
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void eval_reqs();
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void eval_rsps();
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void eval_dram_bus();
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std::queue<core_req_t*> core_req_vec_;
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std::vector<dram_req_t> dram_rsp_vec_;
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std::map<unsigned int, unsigned int*> core_rsp_vec_;
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int dram_rsp_active_;
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uint32_t snp_req_active_;
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uint32_t snp_req_size_;
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uint32_t pending_snp_reqs_;
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VVX_cache *cache_;
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RAM *ram_;
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//#ifdef VCD_OUTPUT
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VerilatedVcdC *trace_;
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//#endif
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};
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