|
configs
|
project directories reorganization
|
2020-04-14 06:35:20 -04:00 |
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models/memory
|
RTL code refactoring
|
2020-04-19 03:38:00 -04:00 |
|
modelsim
|
yosys synthesis refactoring
|
2020-07-10 18:56:41 -04:00 |
|
old_rtl
|
refactoring fixes
|
2020-04-14 19:39:59 -04:00 |
|
opae
|
adding using serial divider to save area cost
|
2020-08-25 02:29:27 -07:00 |
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rtl
|
ibuffer optimization
|
2020-08-26 04:44:36 -07:00 |
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scripts
|
gpr pipeline optimization
|
2020-08-01 12:38:30 -04:00 |
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simulate
|
ibuffer optimization
|
2020-08-26 04:44:36 -07:00 |
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syn
|
ibuffer optimization
|
2020-08-26 04:44:36 -07:00 |
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unit_tests
|
pipeline refactoring - fmax >= 222 mhz
|
2020-08-14 21:50:14 -07:00 |
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Makefile
|
lkg build with pipeline + FPU fixes
|
2020-07-31 09:29:44 -04:00 |
