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https://github.com/vortexgpgpu/vortex.git
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505 lines
No EOL
22 KiB
Verilog
505 lines
No EOL
22 KiB
Verilog
`include "VX_define.vh"
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module Vortex (
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`SCOPE_IO_Vortex
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// Clock
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input wire clk,
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input wire reset,
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// DRAM request
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output wire dram_req_valid,
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output wire dram_req_rw,
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output wire [`VX_DRAM_BYTEEN_WIDTH-1:0] dram_req_byteen,
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output wire [`VX_DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire [`VX_DRAM_LINE_WIDTH-1:0] dram_req_data,
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output wire [`VX_DRAM_TAG_WIDTH-1:0] dram_req_tag,
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input wire dram_req_ready,
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// DRAM response
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input wire dram_rsp_valid,
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input wire [`VX_DRAM_LINE_WIDTH-1:0] dram_rsp_data,
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input wire [`VX_DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
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output wire dram_rsp_ready,
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// Snoop request
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input wire snp_req_valid,
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input wire [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_addr,
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input wire snp_req_inv,
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input wire [`VX_SNP_TAG_WIDTH-1:0] snp_req_tag,
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output wire snp_req_ready,
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// Snoop response
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output wire snp_rsp_valid,
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output wire [`VX_SNP_TAG_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready,
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// I/O request
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output wire [`NUM_THREADS-1:0] io_req_valid,
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output wire io_req_rw,
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output wire [`NUM_THREADS-1:0][3:0] io_req_byteen,
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output wire [`NUM_THREADS-1:0][29:0] io_req_addr,
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output wire [`NUM_THREADS-1:0][31:0] io_req_data,
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output wire [`VX_CORE_TAG_WIDTH-1:0] io_req_tag,
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input wire io_req_ready,
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// I/O response
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input wire io_rsp_valid,
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input wire [31:0] io_rsp_data,
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input wire [`VX_CORE_TAG_WIDTH-1:0] io_rsp_tag,
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output wire io_rsp_ready,
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// CSR I/O Request
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input wire csr_io_req_valid,
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input wire [`VX_CSR_ID_WIDTH-1:0] csr_io_req_coreid,
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input wire [11:0] csr_io_req_addr,
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input wire csr_io_req_rw,
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input wire [31:0] csr_io_req_data,
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output wire csr_io_req_ready,
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// CSR I/O Response
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output wire csr_io_rsp_valid,
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output wire [31:0] csr_io_rsp_data,
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input wire csr_io_rsp_ready,
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// Status
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output wire busy,
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output wire ebreak
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);
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wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid;
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wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag;
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wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_ready;
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wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag;
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wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready;
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wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr;
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wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_inv;
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wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag;
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wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_ready;
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wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_valid;
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wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag;
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wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready;
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wire [`NUM_CLUSTERS-1:0][`NUM_THREADS-1:0] per_cluster_io_req_valid;
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wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_rw;
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wire [`NUM_CLUSTERS-1:0][`NUM_THREADS-1:0][3:0] per_cluster_io_req_byteen;
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wire [`NUM_CLUSTERS-1:0][`NUM_THREADS-1:0][29:0] per_cluster_io_req_addr;
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wire [`NUM_CLUSTERS-1:0][`NUM_THREADS-1:0][31:0] per_cluster_io_req_data;
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wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag;
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wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_ready;
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wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_valid;
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wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag;
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wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_rsp_data;
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wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready;
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wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_valid;
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wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_io_req_addr;
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wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_rw;
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wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_req_data;
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wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_ready;
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wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_valid;
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wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_rsp_data;
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wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_ready;
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wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
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wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak;
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wire [`LOG2UP(`NUM_CLUSTERS)-1:0] csr_io_cluster_id = `LOG2UP(`NUM_CLUSTERS)'(csr_io_req_coreid >> `CLOG2(`NUM_CORES));
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wire [`NC_BITS-1:0] csr_io_core_id = `NC_BITS'(csr_io_req_coreid);
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for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
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VX_cluster #(
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.CLUSTER_ID(i)
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) cluster (
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`SCOPE_BIND_Vortex_cluster(i)
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.clk (clk),
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.reset (reset),
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.dram_req_valid (per_cluster_dram_req_valid [i]),
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.dram_req_rw (per_cluster_dram_req_rw [i]),
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.dram_req_byteen (per_cluster_dram_req_byteen[i]),
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.dram_req_addr (per_cluster_dram_req_addr [i]),
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.dram_req_data (per_cluster_dram_req_data [i]),
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.dram_req_tag (per_cluster_dram_req_tag [i]),
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.dram_req_ready (per_cluster_dram_req_ready [i]),
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.dram_rsp_valid (per_cluster_dram_rsp_valid [i]),
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.dram_rsp_data (per_cluster_dram_rsp_data [i]),
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.dram_rsp_tag (per_cluster_dram_rsp_tag [i]),
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.dram_rsp_ready (per_cluster_dram_rsp_ready [i]),
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.snp_req_valid (per_cluster_snp_req_valid [i]),
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.snp_req_addr (per_cluster_snp_req_addr [i]),
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.snp_req_inv (per_cluster_snp_req_inv [i]),
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.snp_req_tag (per_cluster_snp_req_tag [i]),
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.snp_req_ready (per_cluster_snp_req_ready [i]),
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.snp_rsp_valid (per_cluster_snp_rsp_valid [i]),
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.snp_rsp_tag (per_cluster_snp_rsp_tag [i]),
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.snp_rsp_ready (per_cluster_snp_rsp_ready [i]),
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.io_req_valid (per_cluster_io_req_valid [i]),
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.io_req_rw (per_cluster_io_req_rw [i]),
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.io_req_byteen (per_cluster_io_req_byteen [i]),
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.io_req_addr (per_cluster_io_req_addr [i]),
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.io_req_data (per_cluster_io_req_data [i]),
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.io_req_tag (per_cluster_io_req_tag [i]),
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.io_req_ready (per_cluster_io_req_ready [i]),
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.io_rsp_valid (per_cluster_io_rsp_valid [i]),
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.io_rsp_data (per_cluster_io_rsp_data [i]),
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.io_rsp_tag (per_cluster_io_rsp_tag [i]),
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.io_rsp_ready (per_cluster_io_rsp_ready [i]),
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.csr_io_req_valid (per_cluster_csr_io_req_valid[i]),
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.csr_io_req_coreid (csr_io_core_id),
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.csr_io_req_rw (per_cluster_csr_io_req_rw [i]),
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.csr_io_req_addr (per_cluster_csr_io_req_addr[i]),
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.csr_io_req_data (per_cluster_csr_io_req_data[i]),
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.csr_io_req_ready (per_cluster_csr_io_req_ready[i]),
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.csr_io_rsp_valid (per_cluster_csr_io_rsp_valid[i]),
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.csr_io_rsp_data (per_cluster_csr_io_rsp_data[i]),
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.csr_io_rsp_ready (per_cluster_csr_io_rsp_ready[i]),
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.busy (per_cluster_busy [i]),
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.ebreak (per_cluster_ebreak [i])
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);
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end
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VX_databus_arb #(
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.NUM_REQS (`NUM_CLUSTERS),
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.WORD_SIZE (4),
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.TAG_IN_WIDTH (`L2CORE_TAG_WIDTH),
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.TAG_OUT_WIDTH (`L3CORE_TAG_WIDTH)
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) io_arb (
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.clk (clk),
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.reset (reset),
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// input requests
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.req_valid_in (per_cluster_io_req_valid),
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.req_rw_in (per_cluster_io_req_rw),
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.req_byteen_in (per_cluster_io_req_byteen),
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.req_addr_in (per_cluster_io_req_addr),
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.req_data_in (per_cluster_io_req_data),
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.req_tag_in (per_cluster_io_req_tag),
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.req_ready_in (per_cluster_io_req_ready),
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// output request
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.req_valid_out (io_req_valid),
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.req_rw_out (io_req_rw),
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.req_byteen_out (io_req_byteen),
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.req_addr_out (io_req_addr),
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.req_data_out (io_req_data),
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.req_tag_out (io_req_tag),
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.req_ready_out (io_req_ready),
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// input response
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.rsp_valid_in (io_rsp_valid),
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.rsp_tag_in (io_rsp_tag),
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.rsp_data_in (io_rsp_data),
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.rsp_ready_in (io_rsp_ready),
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// output responses
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.rsp_valid_out (per_cluster_io_rsp_valid),
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.rsp_data_out (per_cluster_io_rsp_data),
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.rsp_tag_out (per_cluster_io_rsp_tag),
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.rsp_ready_out (per_cluster_io_rsp_ready)
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);
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VX_csr_io_arb #(
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.NUM_REQS (`NUM_CLUSTERS),
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.DATA_WIDTH (32),
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.ADDR_WIDTH (12)
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) csr_io_arb (
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.clk (clk),
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.reset (reset),
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.request_id (csr_io_cluster_id),
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// input requests
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.req_valid_in (csr_io_req_valid),
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.req_addr_in (csr_io_req_addr),
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.req_rw_in (csr_io_req_rw),
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.req_data_in (csr_io_req_data),
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.req_ready_in (csr_io_req_ready),
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// output request
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.req_valid_out (per_cluster_csr_io_req_valid),
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.req_addr_out (per_cluster_csr_io_req_addr),
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.req_rw_out (per_cluster_csr_io_req_rw),
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.req_data_out (per_cluster_csr_io_req_data),
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.req_ready_out (per_cluster_csr_io_req_ready),
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// input responses
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.rsp_valid_in (per_cluster_csr_io_rsp_valid),
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.rsp_data_in (per_cluster_csr_io_rsp_data),
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.rsp_ready_in (per_cluster_csr_io_rsp_ready),
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// output response
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.rsp_valid_out (csr_io_rsp_valid),
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.rsp_data_out (csr_io_rsp_data),
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.rsp_ready_out (csr_io_rsp_ready)
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);
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assign busy = (| per_cluster_busy);
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assign ebreak = (| per_cluster_ebreak);
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wire snp_fwd_rsp_valid;
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wire [`L3DRAM_ADDR_WIDTH-1:0] snp_fwd_rsp_addr;
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wire snp_fwd_rsp_inv;
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wire [`L3SNP_TAG_WIDTH-1:0] snp_fwd_rsp_tag;
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wire snp_fwd_rsp_ready;
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VX_snp_forwarder #(
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.CACHE_ID (`L3CACHE_ID),
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.NUM_REQS (`NUM_CLUSTERS),
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.SRC_ADDR_WIDTH (`L3DRAM_ADDR_WIDTH),
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.DST_ADDR_WIDTH (`L2DRAM_ADDR_WIDTH),
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.TAG_IN_WIDTH (`L3SNP_TAG_WIDTH),
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.TAG_OUT_WIDTH (`L2SNP_TAG_WIDTH),
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.SREQ_SIZE (`L3SREQ_SIZE)
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) snp_forwarder (
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.clk (clk),
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.reset (reset),
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.snp_req_valid (snp_req_valid),
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.snp_req_addr (snp_req_addr),
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.snp_req_inv (snp_req_inv),
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.snp_req_tag (snp_req_tag),
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.snp_req_ready (snp_req_ready),
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.snp_rsp_valid (snp_fwd_rsp_valid),
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.snp_rsp_addr (snp_fwd_rsp_addr),
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.snp_rsp_inv (snp_fwd_rsp_inv),
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.snp_rsp_tag (snp_fwd_rsp_tag),
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.snp_rsp_ready (snp_fwd_rsp_ready),
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.snp_fwdout_valid (per_cluster_snp_req_valid),
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.snp_fwdout_addr (per_cluster_snp_req_addr),
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.snp_fwdout_inv (per_cluster_snp_req_inv),
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.snp_fwdout_tag (per_cluster_snp_req_tag),
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.snp_fwdout_ready (per_cluster_snp_req_ready),
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.snp_fwdin_valid (per_cluster_snp_rsp_valid),
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.snp_fwdin_tag (per_cluster_snp_rsp_tag),
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.snp_fwdin_ready (per_cluster_snp_rsp_ready)
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);
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if (`L3_ENABLE) begin
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_l3cache_if();
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`endif
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wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid_qual;
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wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw_qual;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen_qual;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr_qual;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data_qual;
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wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag_qual;
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wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_ready_qual;
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for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
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VX_skid_buffer #(
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.DATAW (1 + `L2DRAM_BYTEEN_WIDTH + `L2DRAM_ADDR_WIDTH + `L2DRAM_LINE_WIDTH + `L2DRAM_TAG_WIDTH),
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.PASSTHRU (`NUM_CLUSTERS < 4)
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) dram_req_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (per_cluster_dram_req_valid[i]),
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.data_in ({per_cluster_dram_req_rw[i], per_cluster_dram_req_byteen[i], per_cluster_dram_req_addr[i], per_cluster_dram_req_data[i], per_cluster_dram_req_tag[i]}),
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.ready_in (per_cluster_dram_req_ready[i]),
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.valid_out (per_cluster_dram_req_valid_qual[i]),
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.data_out ({per_cluster_dram_req_rw_qual[i], per_cluster_dram_req_byteen_qual[i], per_cluster_dram_req_addr_qual[i], per_cluster_dram_req_data_qual[i], per_cluster_dram_req_tag_qual[i]}),
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.ready_out (per_cluster_dram_req_ready_qual[i])
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);
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end
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VX_cache #(
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.CACHE_ID (`L3CACHE_ID),
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.CACHE_SIZE (`L3CACHE_SIZE),
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.BANK_LINE_SIZE (`L3BANK_LINE_SIZE),
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.NUM_BANKS (`L3NUM_BANKS),
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.WORD_SIZE (`L3WORD_SIZE),
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.NUM_REQS (`NUM_CLUSTERS),
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.CREQ_SIZE (`L3CREQ_SIZE),
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.MSHR_SIZE (`L3MSHR_SIZE),
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.DRSQ_SIZE (`L3DRSQ_SIZE),
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.SREQ_SIZE (`L3SREQ_SIZE),
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.CRSQ_SIZE (`L3CRSQ_SIZE),
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.DREQ_SIZE (`L3DREQ_SIZE),
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.SRSQ_SIZE (`L3SRSQ_SIZE),
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.DRAM_ENABLE (1),
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.FLUSH_ENABLE (1),
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.WRITE_ENABLE (1),
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.CORE_TAG_WIDTH (`L2DRAM_TAG_WIDTH),
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.CORE_TAG_ID_BITS (0),
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.DRAM_TAG_WIDTH (`L3DRAM_TAG_WIDTH),
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.SNP_TAG_WIDTH (`L3SNP_TAG_WIDTH)
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) l3cache (
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`SCOPE_BIND_Vortex_l3cache
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.clk (clk),
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.reset (reset),
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`ifdef PERF_ENABLE
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.perf_cache_if (perf_l3cache_if),
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`endif
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// Core request
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.core_req_valid (per_cluster_dram_req_valid_qual),
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.core_req_rw (per_cluster_dram_req_rw_qual),
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.core_req_byteen (per_cluster_dram_req_byteen_qual),
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.core_req_addr (per_cluster_dram_req_addr_qual),
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.core_req_data (per_cluster_dram_req_data_qual),
|
|
.core_req_tag (per_cluster_dram_req_tag_qual),
|
|
.core_req_ready (per_cluster_dram_req_ready_qual),
|
|
|
|
// Core response
|
|
.core_rsp_valid (per_cluster_dram_rsp_valid),
|
|
.core_rsp_data (per_cluster_dram_rsp_data),
|
|
.core_rsp_tag (per_cluster_dram_rsp_tag),
|
|
.core_rsp_ready (per_cluster_dram_rsp_ready),
|
|
|
|
// DRAM request
|
|
.dram_req_valid (dram_req_valid),
|
|
.dram_req_rw (dram_req_rw),
|
|
.dram_req_byteen (dram_req_byteen),
|
|
.dram_req_addr (dram_req_addr),
|
|
.dram_req_data (dram_req_data),
|
|
.dram_req_tag (dram_req_tag),
|
|
.dram_req_ready (dram_req_ready),
|
|
|
|
// DRAM response
|
|
.dram_rsp_valid (dram_rsp_valid),
|
|
.dram_rsp_data (dram_rsp_data),
|
|
.dram_rsp_tag (dram_rsp_tag),
|
|
.dram_rsp_ready (dram_rsp_ready),
|
|
|
|
// Snoop request
|
|
.snp_req_valid (snp_fwd_rsp_valid),
|
|
.snp_req_addr (snp_fwd_rsp_addr),
|
|
.snp_req_inv (snp_fwd_rsp_inv),
|
|
.snp_req_tag (snp_fwd_rsp_tag),
|
|
.snp_req_ready (snp_fwd_rsp_ready),
|
|
|
|
// Snoop response
|
|
.snp_rsp_valid (snp_rsp_valid),
|
|
.snp_rsp_tag (snp_rsp_tag),
|
|
.snp_rsp_ready (snp_rsp_ready),
|
|
|
|
// Miss status
|
|
`UNUSED_PIN (miss_vec)
|
|
);
|
|
|
|
end else begin
|
|
|
|
VX_mem_arb #(
|
|
.NUM_REQS (`NUM_CLUSTERS),
|
|
.DATA_WIDTH (`L3DRAM_LINE_WIDTH),
|
|
.TAG_IN_WIDTH (`L2DRAM_TAG_WIDTH),
|
|
.TAG_OUT_WIDTH (`L3DRAM_TAG_WIDTH)
|
|
) dram_arb (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
|
|
// Core request
|
|
.req_valid_in (per_cluster_dram_req_valid),
|
|
.req_rw_in (per_cluster_dram_req_rw),
|
|
.req_byteen_in (per_cluster_dram_req_byteen),
|
|
.req_addr_in (per_cluster_dram_req_addr),
|
|
.req_data_in (per_cluster_dram_req_data),
|
|
.req_tag_in (per_cluster_dram_req_tag),
|
|
.req_ready_in (per_cluster_dram_req_ready),
|
|
|
|
// DRAM request
|
|
.req_valid_out (dram_req_valid),
|
|
.req_rw_out (dram_req_rw),
|
|
.req_byteen_out (dram_req_byteen),
|
|
.req_addr_out (dram_req_addr),
|
|
.req_data_out (dram_req_data),
|
|
.req_tag_out (dram_req_tag),
|
|
.req_ready_out (dram_req_ready),
|
|
|
|
// Core response
|
|
.rsp_valid_out (per_cluster_dram_rsp_valid),
|
|
.rsp_data_out (per_cluster_dram_rsp_data),
|
|
.rsp_tag_out (per_cluster_dram_rsp_tag),
|
|
.rsp_ready_out (per_cluster_dram_rsp_ready),
|
|
|
|
// DRAM response
|
|
.rsp_valid_in (dram_rsp_valid),
|
|
.rsp_tag_in (dram_rsp_tag),
|
|
.rsp_data_in (dram_rsp_data),
|
|
.rsp_ready_in (dram_rsp_ready)
|
|
);
|
|
|
|
`UNUSED_VAR (snp_fwd_rsp_addr)
|
|
`UNUSED_VAR (snp_fwd_rsp_inv)
|
|
|
|
assign snp_rsp_valid = snp_fwd_rsp_valid;
|
|
assign snp_rsp_tag = snp_fwd_rsp_tag;
|
|
assign snp_fwd_rsp_ready = snp_rsp_ready;
|
|
|
|
end
|
|
|
|
`SCOPE_ASSIGN (reset, reset);
|
|
|
|
`SCOPE_ASSIGN (dram_req_fire, dram_req_valid && dram_req_ready);
|
|
`SCOPE_ASSIGN (dram_req_addr, `TO_FULL_ADDR(dram_req_addr));
|
|
`SCOPE_ASSIGN (dram_req_rw, dram_req_rw);
|
|
`SCOPE_ASSIGN (dram_req_byteen,dram_req_byteen);
|
|
`SCOPE_ASSIGN (dram_req_data, dram_req_data);
|
|
`SCOPE_ASSIGN (dram_req_tag, dram_req_tag);
|
|
|
|
`SCOPE_ASSIGN (dram_rsp_fire, dram_rsp_valid && dram_rsp_ready);
|
|
`SCOPE_ASSIGN (dram_rsp_data, dram_rsp_data);
|
|
`SCOPE_ASSIGN (dram_rsp_tag, dram_rsp_tag);
|
|
|
|
`SCOPE_ASSIGN (snp_req_fire, snp_req_valid && snp_req_ready);
|
|
`SCOPE_ASSIGN (snp_req_addr, `TO_FULL_ADDR(snp_req_addr));
|
|
`SCOPE_ASSIGN (snp_req_inv, snp_req_inv);
|
|
`SCOPE_ASSIGN (snp_req_tag, snp_req_tag);
|
|
|
|
`SCOPE_ASSIGN (snp_rsp_fire, snp_rsp_valid && snp_rsp_ready);
|
|
`SCOPE_ASSIGN (snp_rsp_tag, snp_rsp_tag);
|
|
|
|
`SCOPE_ASSIGN (snp_rsp_fire, snp_rsp_valid && snp_rsp_ready);
|
|
`SCOPE_ASSIGN (snp_rsp_tag, snp_rsp_tag);
|
|
|
|
`SCOPE_ASSIGN (busy, busy);
|
|
|
|
`ifdef DBG_PRINT_DRAM
|
|
always @(posedge clk) begin
|
|
if (dram_req_valid && dram_req_ready) begin
|
|
if (dram_req_rw)
|
|
$display("%t: DRAM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen, dram_req_data);
|
|
else
|
|
$display("%t: DRAM Rd Req: addr=%0h, tag=%0h, byteen=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen);
|
|
end
|
|
if (dram_rsp_valid && dram_rsp_ready) begin
|
|
$display("%t: DRAM Rsp: tag=%0h, data=%0h", $time, dram_rsp_tag, dram_rsp_data);
|
|
end
|
|
end
|
|
`endif
|
|
|
|
|
|
`ifndef NDEBUG
|
|
always @(posedge clk) begin
|
|
$fflush(); // flush stdout buffer
|
|
end
|
|
`endif
|
|
|
|
endmodule |