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32 lines
No EOL
734 B
Verilog
32 lines
No EOL
734 B
Verilog
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module VX_generic_stack #(
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parameter WIDTH = 1,
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parameter DEPTH = 1
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) (
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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input reg [WIDTH - 1:0] q1,
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input reg [WIDTH - 1:0] q2,
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output wire[WIDTH - 1:0] d
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);
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reg [DEPTH - 1:0] ptr;
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reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
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always @(posedge clk) begin
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if (reset) begin
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ptr <= 0;
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end else if (push) begin
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stack[ptr] <= q1;
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stack[ptr+1] <= q2;
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ptr <= ptr + 2;
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end else if (pop) begin
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ptr <= ptr - 1;
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end
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end
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assign d = stack[ptr - 1];
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endmodule |