mirror of
https://github.com/vortexgpgpu/vortex.git
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323 lines
8.2 KiB
C++
323 lines
8.2 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "func_unit.h"
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#include <iostream>
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#include <iomanip>
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#include <string.h>
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#include <assert.h>
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#include <util.h>
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#include "debug.h"
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#include "core.h"
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#include "constants.h"
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#include "cache_sim.h"
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#define GROUPS
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// #define DEFAULT
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using namespace vortex;
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AluUnit::AluUnit(const SimContext& ctx, Core* core) : FuncUnit(ctx, core, "ALU") {}
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void AluUnit::tick() {
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for (uint32_t iw = 0; iw < ISSUE_WIDTH; ++iw) {
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auto& input = Inputs.at(iw);
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if (input.empty())
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continue;
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auto& output = Outputs.at(iw);
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auto trace = input.front();
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switch (trace->alu_type) {
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case AluType::ARITH:
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case AluType::BRANCH:
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case AluType::SYSCALL:
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case AluType::IMUL:
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output.push(trace, LATENCY_IMUL+1);
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break;
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case AluType::IDIV:
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output.push(trace, XLEN+1);
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break;
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case AluType::VOTE:
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case AluType::SHFL:
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output.push(trace, 1);
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break;
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default:
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std::abort();
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}
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DT(3, "pipeline-execute: op=" << trace->alu_type << ", " << *trace);
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if (trace->eop && trace->fetch_stall) {
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core_->resume(trace->wid);
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}
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input.pop();
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}
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}
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///////////////////////////////////////////////////////////////////////////////
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FpuUnit::FpuUnit(const SimContext& ctx, Core* core) : FuncUnit(ctx, core, "FPU") {}
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void FpuUnit::tick() {
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for (uint32_t iw = 0; iw < ISSUE_WIDTH; ++iw) {
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auto& input = Inputs.at(iw);
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if (input.empty())
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continue;
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auto& output = Outputs.at(iw);
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auto trace = input.front();
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switch (trace->fpu_type) {
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case FpuType::FNCP:
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output.push(trace, 2);
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break;
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case FpuType::FMA:
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output.push(trace, LATENCY_FMA+1);
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break;
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case FpuType::FDIV:
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output.push(trace, LATENCY_FDIV+1);
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break;
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case FpuType::FSQRT:
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output.push(trace, LATENCY_FSQRT+1);
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break;
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case FpuType::FCVT:
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output.push(trace, LATENCY_FCVT+1);
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break;
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default:
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std::abort();
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}
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DT(3, "pipeline-execute: op=" << trace->fpu_type << ", " << *trace);
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input.pop();
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}
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}
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///////////////////////////////////////////////////////////////////////////////
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LsuUnit::LsuUnit(const SimContext& ctx, Core* core)
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: FuncUnit(ctx, core, "LSU")
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, pending_loads_(0)
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{}
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LsuUnit::~LsuUnit()
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{}
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void LsuUnit::reset() {
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for (auto& state : states_) {
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state.clear();
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}
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pending_loads_ = 0;
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}
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void LsuUnit::tick() {
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core_->perf_stats_.load_latency += pending_loads_;
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// handle memory responses
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for (uint32_t r = 0; r < LSU_NUM_REQS; ++r) {
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auto& dcache_rsp_port = core_->lsu_demux_.at(r)->RspIn;
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if (dcache_rsp_port.empty())
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continue;
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uint32_t block_idx = r / LSU_CHANNELS;
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auto& state = states_.at(block_idx);
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auto& mem_rsp = dcache_rsp_port.front();
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auto& entry = state.pending_rd_reqs.at(mem_rsp.tag);
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auto trace = entry.trace;
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DT(3, "mem-rsp: tag=" << mem_rsp.tag << ", type=" << trace->lsu_type << ", rid=" << r << ", " << *trace);
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assert(entry.count);
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--entry.count; // track remaining addresses
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if (0 == entry.count) {
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int iw = trace->wid % ISSUE_WIDTH;
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Outputs.at(iw).push(trace, 1);
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state.pending_rd_reqs.release(mem_rsp.tag);
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}
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dcache_rsp_port.pop();
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--pending_loads_;
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}
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// handle LSU requests
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for (uint32_t iw = 0; iw < ISSUE_WIDTH; ++iw) {
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uint32_t block_idx = iw % NUM_LSU_BLOCKS;
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auto& state = states_.at(block_idx);
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if (state.fence_lock) {
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// wait for all pending memory operations to complete
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if (!state.pending_rd_reqs.empty())
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continue;
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Outputs.at(iw).push(state.fence_trace, 1);
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state.fence_lock = false;
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DT(3, "fence-unlock: " << state.fence_trace);
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}
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// check input queue
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auto& input = Inputs.at(iw);
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if (input.empty())
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continue;
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auto& output = Outputs.at(iw);
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auto trace = input.front();
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if (trace->lsu_type == LsuType::FENCE) {
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// schedule fence lock
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state.fence_trace = trace;
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state.fence_lock = true;
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DT(3, "fence-lock: " << *trace);
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// remove input
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input.pop();
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continue;
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}
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bool is_write = (trace->lsu_type == LsuType::STORE);
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// check pending queue capacity
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if (!is_write && state.pending_rd_reqs.full()) {
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if (!trace->log_once(true)) {
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DT(4, "*** " << this->name() << "-queue-full: " << *trace);
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}
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continue;
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} else {
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trace->log_once(false);
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}
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uint32_t tag = 0;
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if (!is_write) {
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tag = state.pending_rd_reqs.allocate({trace, 0});
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}
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// send memory request
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auto num_reqs = this->send_requests(trace, block_idx, tag);
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if (!is_write) {
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state.pending_rd_reqs.at(tag).count = num_reqs;
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}
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// do not wait on writes
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if (is_write) {
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output.push(trace, 1);
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}
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// remove input
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input.pop();
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}
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}
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int LsuUnit::send_requests(instr_trace_t* trace, int block_idx, int tag) {
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int count = 0;
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auto trace_data = std::dynamic_pointer_cast<LsuTraceData>(trace->data);
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bool is_write = (trace->lsu_type == LsuType::STORE);
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auto t0 = trace->pid * NUM_LSU_LANES;
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for (uint32_t i = 0; i < NUM_LSU_LANES; ++i) {
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uint32_t t = t0 + i;
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if (!trace->tmask.test(t))
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continue;
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int req_idx = block_idx * LSU_CHANNELS + (i % LSU_CHANNELS);
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auto& dcache_req_port = core_->lsu_demux_.at(req_idx)->ReqIn;
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auto mem_addr = trace_data->mem_addrs.at(t);
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auto type = get_addr_type(mem_addr.addr);
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MemReq mem_req;
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mem_req.addr = mem_addr.addr;
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mem_req.write = is_write;
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mem_req.type = type;
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mem_req.tag = tag;
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mem_req.cid = trace->cid;
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mem_req.uuid = trace->uuid;
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dcache_req_port.push(mem_req, 1);
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DT(3, "mem-req: addr=0x" << std::hex << mem_req.addr << ", tag=" << tag
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<< ", lsu_type=" << trace->lsu_type << ", rid=" << req_idx << ", addr_type=" << mem_req.type << ", " << *trace);
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if (is_write) {
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++core_->perf_stats_.stores;
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} else {
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++core_->perf_stats_.loads;
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++pending_loads_;
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}
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++count;
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}
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return count;
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}
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///////////////////////////////////////////////////////////////////////////////
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SfuUnit::SfuUnit(const SimContext& ctx, Core* core)
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: FuncUnit(ctx, core, "SFU")
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{}
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void SfuUnit::tick() {
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// check input queue
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for (uint32_t iw = 0; iw < ISSUE_WIDTH; ++iw) {
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auto& input = Inputs.at(iw);
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if (input.empty())
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continue;
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auto& output = Outputs.at(iw);
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auto trace = input.front();
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auto sfu_type = trace->sfu_type;
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bool release_warp = trace->fetch_stall;
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switch (sfu_type) {
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case SfuType::WSPAWN:
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output.push(trace, 1);
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if (trace->eop) {
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auto trace_data = std::dynamic_pointer_cast<SFUTraceData>(trace->data);
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release_warp = core_->wspawn(trace_data->arg1, trace_data->arg2);
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}
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break;
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case SfuType::TMC:
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case SfuType::SPLIT:
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case SfuType::JOIN:
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case SfuType::PRED:
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case SfuType::CSRRW:
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case SfuType::CSRRS:
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case SfuType::CSRRC:
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output.push(trace, 1);
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break;
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case SfuType::BAR: {
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output.push(trace, 1);
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if (trace->eop) {
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auto trace_data = std::dynamic_pointer_cast<SFUTraceData>(trace->data);
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#ifdef DEFAULT
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release_warp = core_->barrier(trace_data->arg1, trace_data->arg2, trace->wid);
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#endif
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#ifdef GROUPS
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std::bitset<32> mask = trace_data->arg2;
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int count = mask.count();
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DT(1, "MASK, COUNT" << mask << ", " << count<< "," <<MAX_NUMBER_TILES - 1 - 4);
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for (size_t warp_id = 0, nw = MAX_NUMBER_TILES; warp_id < nw; ++warp_id) {
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if(mask.test(MAX_NUMBER_TILES - 1 - warp_id))
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release_warp &= core_->barrier(trace_data->arg1, count, warp_id);
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}
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#endif
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}
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} break;
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case SfuType::TILE:{
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output.push(trace, 1);
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if (trace->eop) {
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auto trace_data = std::dynamic_pointer_cast<SFUTraceData>(trace->data);
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auto tile_mask = trace_data->arg1;
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auto thread_count = trace_data->arg2;
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release_warp = core_->tileMask(tile_mask, thread_count);
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}
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}
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break;
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default:
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std::abort();
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}
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DT(3, "pipeline-execute: op=" << trace->sfu_type << ", " << *trace);
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if (trace->eop && release_warp) {
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DT(3, "pipeline-ssfdsdssdsd: op=" << trace->sfu_type << ", " << *trace);
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core_->resume(trace->wid);
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}
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input.pop();
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}
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}
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