mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 22:07:41 -04:00
356 lines
No EOL
8.8 KiB
C++
356 lines
No EOL
8.8 KiB
C++
#include "simulator.h"
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#include <iostream>
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#include <fstream>
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#include <iomanip>
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uint64_t timestamp = 0;
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double sc_time_stamp() {
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return timestamp;
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}
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Simulator::Simulator() {
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// force random values for unitialized signals
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Verilated::randReset(2);
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// Turn off assertion before reset
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Verilated::assertOn(false);
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ram_ = nullptr;
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vortex_ = new VVortex();
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dram_rsp_active_ = false;
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snp_req_active_ = false;
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#ifdef VCD_OUTPUT
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Verilated::traceEverOn(true);
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trace_ = new VerilatedVcdC();
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trace_->set_time_unit("1ns");
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vortex_->trace(trace_, 99);
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trace_->open("trace.vcd");
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#endif
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}
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Simulator::~Simulator() {
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#ifdef VCD_OUTPUT
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trace_->close();
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#endif
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delete vortex_;
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}
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void Simulator::attach_ram(RAM* ram) {
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ram_ = ram;
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dram_rsp_vec_.clear();
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}
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void Simulator::reset() {
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#ifndef NDEBUG
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std::cout << timestamp << ": [sim] reset()" << std::endl;
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#endif
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vortex_->reset = 1;
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this->step();
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vortex_->reset = 0;
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dram_rsp_vec_.clear();
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// Turn on assertion after reset
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Verilated::assertOn(true);
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}
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void Simulator::step() {
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vortex_->clk = 0;
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this->eval();
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vortex_->clk = 1;
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this->eval();
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this->eval_dram_bus();
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this->eval_io_bus();
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this->eval_csr_bus();
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this->eval_snp_bus();
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}
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void Simulator::eval() {
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vortex_->eval();
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#ifdef VCD_OUTPUT
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trace_->dump(timestamp);
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#endif
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++timestamp;
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}
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void Simulator::eval_dram_bus() {
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if (ram_ == nullptr) {
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vortex_->dram_req_ready = 0;
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return;
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}
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// schedule DRAM responses
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int dequeue_index = -1;
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for (int i = 0; i < dram_rsp_vec_.size(); i++) {
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if (dram_rsp_vec_[i].cycles_left > 0) {
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dram_rsp_vec_[i].cycles_left -= 1;
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}
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if ((dequeue_index == -1)
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&& (dram_rsp_vec_[i].cycles_left == 0)) {
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dequeue_index = i;
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}
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}
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// send DRAM response
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if (dram_rsp_active_
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&& vortex_->dram_rsp_valid
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&& vortex_->dram_rsp_ready) {
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dram_rsp_active_ = false;
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}
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if (!dram_rsp_active_) {
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if (dequeue_index != -1) {
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vortex_->dram_rsp_valid = 1;
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memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].block.data(), GLOBAL_BLOCK_SIZE);
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vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;
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dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
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dram_rsp_active_ = true;
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} else {
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vortex_->dram_rsp_valid = 0;
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}
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}
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// handle DRAM stalls
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bool dram_stalled = false;
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#ifdef ENABLE_DRAM_STALLS
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if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) {
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dram_stalled = true;
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} else
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if (dram_rsp_vec_.size() >= DRAM_RQ_SIZE) {
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dram_stalled = true;
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}
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#endif
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// process DRAM requests
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if (!dram_stalled) {
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if (vortex_->dram_req_valid) {
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if (vortex_->dram_req_rw) {
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uint64_t byteen = vortex_->dram_req_byteen;
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unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
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uint8_t* data = (uint8_t*)(vortex_->dram_req_data);
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for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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(*ram_)[base_addr + i] = data[i];
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}
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}
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} else {
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dram_req_t dram_req;
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dram_req.cycles_left = DRAM_LATENCY;
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dram_req.tag = vortex_->dram_req_tag;
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ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.block.data());
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dram_rsp_vec_.push_back(dram_req);
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}
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}
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}
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vortex_->dram_req_ready = ~dram_stalled;
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}
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void Simulator::eval_io_bus() {
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if (vortex_->io_req_valid
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&& vortex_->io_req_rw
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&& ((vortex_->io_req_addr << 2) == IO_BUS_ADDR_COUT)) {
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uint32_t data_write = (uint32_t)vortex_->io_req_data;
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char c = (char)data_write;
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std::cout << c;
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}
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vortex_->io_req_ready = 1;
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vortex_->io_rsp_valid = 0;
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}
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void Simulator::eval_csr_bus() {
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vortex_->csr_io_req_valid = 0;
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vortex_->csr_io_req_coreid = 0;
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vortex_->csr_io_req_addr = 0;
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vortex_->csr_io_req_rw = 0;
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vortex_->csr_io_req_data = 0;
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vortex_->csr_io_rsp_ready = 1;
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}
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void Simulator::eval_snp_bus() {
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if (snp_req_active_) {
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if (vortex_->snp_rsp_valid) {
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assert(pending_snp_reqs_ > 0);
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--pending_snp_reqs_;
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#ifdef DBG_PRINT_CACHE_SNP
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std::cout << timestamp << ": [sim] snp rsp: tag=" << vortex_->snp_rsp_tag << " pending=" << pending_snp_reqs_ << std::endl;
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#endif
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}
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if (vortex_->snp_req_valid && vortex_->snp_req_ready) {
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if (snp_req_size_) {
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vortex_->snp_req_addr += 1;
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vortex_->snp_req_tag += 1;
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--snp_req_size_;
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++pending_snp_reqs_;
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#ifdef DBG_PRINT_CACHE_SNP
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std::cout << timestamp << ": [sim] snp req: addr=" << std::hex << vortex_->snp_req_addr << std::dec << " tag=" << vortex_->snp_req_tag << " remain=" << snp_req_size_ << std::endl;
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#endif
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} else {
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vortex_->snp_req_valid = 0;
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}
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}
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if (!vortex_->snp_req_valid
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&& 0 == pending_snp_reqs_) {
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snp_req_active_ = false;
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}
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} else {
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vortex_->snp_req_valid = 0;
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vortex_->snp_rsp_ready = 0;
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}
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}
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void Simulator::wait(uint32_t cycles) {
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for (int i = 0; i < cycles; ++i) {
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this->step();
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}
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}
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bool Simulator::is_busy() {
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return vortex_->busy || snp_req_active_;
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}
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void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
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#ifndef NDEBUG
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std::cout << timestamp << ": [sim] flush_caches()" << std::endl;
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#endif
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if (0 == size)
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return;
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snp_req_active_ = true;
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snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE;
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vortex_->snp_req_addr = mem_addr / GLOBAL_BLOCK_SIZE;
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vortex_->snp_req_tag = 0;
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vortex_->snp_req_valid = 1;
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vortex_->snp_rsp_ready = 1;
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--snp_req_size_;
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pending_snp_reqs_ = 1;
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#ifdef DBG_PRINT_CACHE_SNP
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std::cout << timestamp << ": [sim] snp req: addr=" << std::hex << vortex_->snp_req_addr << std::dec << " tag=" << vortex_->snp_req_tag << " remain=" << snp_req_size_ << std::endl;
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#endif
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}
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void Simulator::run() {
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#ifndef NDEBUG
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std::cout << timestamp << ": [sim] run()" << std::endl;
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#endif
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// reset the device
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this->reset();
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// execute program
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while (vortex_->busy
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&& !vortex_->ebreak) {
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this->step();
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}
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// wait 5 cycles to flush the pipeline
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this->wait(5);
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}
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int Simulator::get_status(int reg) {
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// check riscv-tests PASSED/FAILED status
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#if (NUM_CLUSTERS == 1 && NUM_CORES == 1)
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return (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb[reg];
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#elif (NUM_CLUSTERS == 1)
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return (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb[reg];
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#else
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return (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb[reg];
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#endif
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}
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void Simulator::load_bin(const char* program_file) {
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if (ram_ == nullptr)
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return;
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std::ifstream ifs(program_file);
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if (!ifs) {
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std::cout << "error: " << program_file << " not found" << std::endl;
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}
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ifs.seekg(0, ifs.end);
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auto size = ifs.tellg();
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std::vector<uint8_t> content(size);
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ifs.seekg(0, ifs.beg);
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ifs.read((char*)content.data(), size);
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ram_->write(STARTUP_ADDR, size, content.data());
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}
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void Simulator::load_ihex(const char* program_file) {
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if (ram_ == nullptr)
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return;
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auto hti = [&](char c)->uint32_t {
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if (c >= 'A' && c <= 'F')
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return c - 'A' + 10;
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if (c >= 'a' && c <= 'f')
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return c - 'a' + 10;
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return c - '0';
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};
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auto hToI = [&](const char *c, uint32_t size)->uint32_t {
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uint32_t value = 0;
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for (uint32_t i = 0; i < size; i++) {
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value += hti(c[i]) << ((size - i - 1) * 4);
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}
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return value;
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};
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std::ifstream ifs(program_file);
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if (!ifs) {
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std::cout << "error: " << program_file << " not found" << std::endl;
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}
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ifs.seekg(0, ifs.end);
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uint32_t size = ifs.tellg();
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std::vector<char> content(size);
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ifs.seekg(0, ifs.beg);
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ifs.read(content.data(), size);
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int offset = 0;
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char *line = content.data();
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while (true) {
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if (line[0] == ':') {
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uint32_t byteCount = hToI(line + 1, 2);
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uint32_t nextAddr = hToI(line + 3, 4) + offset;
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uint32_t key = hToI(line + 7, 2);
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switch (key) {
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case 0:
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for (uint32_t i = 0; i < byteCount; i++) {
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(*ram_)[nextAddr + i] = hToI(line + 9 + i * 2, 2);
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}
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break;
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case 2:
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offset = hToI(line + 9, 4) << 4;
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break;
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case 4:
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offset = hToI(line + 9, 4) << 16;
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break;
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default:
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break;
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}
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}
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while (*line != '\n' && size != 0) {
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++line;
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--size;
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}
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if (size <= 1)
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break;
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++line;
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--size;
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}
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}
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void Simulator::print_stats(std::ostream& out) {
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out << std::left;
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out << std::setw(24) << "# of total cycles:" << std::dec << timestamp/2 << std::endl;
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} |