fares 9e58bf8fb5 Started synthesis script		2019-11-22 00:32:19 -05:00
..
191017.log	added log file	2019-10-17 14:00:22 -04:00
cshrc.dc	Added fsyn for my synthesis	2019-10-27 22:16:57 -04:00
dc.log	Added dc.log	2019-11-11 14:30:14 -05:00
dc_1GHz.log	Finished synthesis at 1GHz, cell count increases to 1870k	2019-10-29 11:33:23 -04:00
dc_noOpt.log	Finished synthesis with no optimization, cell count increasts to 100k	2019-10-21 17:53:51 -04:00
esyn.tcl	8Warp 32Threads for GTCAD synthesis	2019-11-21 23:51:11 -05:00
fsyn.tcl	Fixed AA d_cache sizing errors	2019-11-11 15:20:58 -05:00
Makefile	Synthesis Compatible	2019-11-21 21:43:43 -05:00
NanGate_15nm_OCL.db	Added fsyn for my synthesis	2019-10-27 22:16:57 -04:00
run_mult_synth.sh	Started synthesis script	2019-11-22 00:32:19 -05:00
syn.tcl	Set associative bank working	2019-10-30 14:57:20 -04:00
Vortex.ddc	Included the SDC and DDC files	2019-10-28 17:24:19 -04:00
Vortex.netlist.v	Added the synthesis netlist	2019-10-28 17:11:15 -04:00
Vortex.sdc	Included the SDC and DDC files	2019-10-28 17:24:19 -04:00
vortex_syn.log	Added a pipeline stage + fixed SM param errors	2019-11-13 12:25:28 -05:00