generated from rit-ecet-notes/new-course
84 lines
3.3 KiB
Markdown
84 lines
3.3 KiB
Markdown
# Design vs Implementation
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Most of the previous courses are implementation-based. This course, and ESD I/II are primarily design based.
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Do not simply code a solution. Design your solution first.
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Research Open Source multichannel oscilloscope using an arduino
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## Syllabus Overview
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We will spend a significant poriton of the courses on testbenches, due to the lack of coverage in previous courses.
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"I don't give a lot of homework.": Syllabus lists one assignment approximately every 3 weeks. Late homework will not be accepted.
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Quizzes will be given, both announced and unannounced, thorughout the semester. Quizzes are closed book closed note.
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***YOU MUST PASS THE LAB TO PASS THE CLASS.***
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Attendance is optional.
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There will be 3 exams, including the final. 1x 8.5"x11" sheet of handwritten notes is allowed.
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## HDL Basics
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HDL = Hardware Description Language
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Unlike most code, HDL code is *concurrent, rather than sequential*.
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HDL, due to being concurrent, is *low-latency*.
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Textbook ("Effective Coding in VHDL" by Ricardo Jasinski) is optional, but has important design concepts.
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There are two primary languages in HDL:
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- VHDL
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- Verilog
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SystemVerilog is also extant, and appears to use both VHDL and Verilog, with portions of C++ as well.
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Professor appears to enjoy Elon Musk's work. Professor is also somewhat scatterbrained. Determining eye contact is somewhat unclear from the back of the lecture room. However, he does appear to know many people in the industry.
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*determinism*:
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*clock*:
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*memory*:
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*computer*: the combination of input, output, processing, and memory. Note that this does not require the computer to be DIGITAL.
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In lab, we will be working from the bare basics. We will implement an adder, then move beyond that.
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No lab for the first two weeks.
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---
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This professor enjoys analysing precisely what words mean. He also is pushing "climb-the-ladder" mindset.
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Microprocessors contain memory, a program counter, and a series of instructions.
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FPGA's, by contrast, are staticly defined gates that will always perform the exact same programmed task.I see. That makes sense.
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Microprocessors run 10x faster than an FPGA. However, FPGA's are more parallelised.
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---
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Combinational logic is asynchronous. That is not to say instantaneously, however it is not clock dependent. This is code that can be performed concurrently.
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Synchronous, by contrast, requires a clock signal. This is slower, but is perhaps safer, due to ignoring most instances of transition and debounce. This is code that can only be performed sequentially, in a `process` codeblock.
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There is propogation delays between each logical transition, but its rather minute so in most cases can be ignored. However, this shows up more prevalently in simulations, and is defined as Delta Time.
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Processes work off of snapshots in time. Cascading assignments within processes may not work as expected.
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---
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As with any other language, there are multiple ways to implement the same idea.
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---
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Elecrtical systems internally contain similar behaviour to physical debounce.
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Asynchronous operations should be pre-registered and post-registered.
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`generate` statements are similar to generics, and are often used in conjunction with generics. There are also `for` loop generate statements. The main usecase for generate statements is for debugging.
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