rit-ecet-notes/cpet-561-01l1
2
0
Fork 0
generated from rit-ecet-notes/new-course
Code Issues Pull requests Projects Releases Packages Wiki Activity
Embedded Systems Design 1 Lab
4 commits 1 branch 0 tags 102 MiB
Find a file
Exact
Blizzard Finnegan 1e81b63298
 Organise distributed files for lab1
2024-08-26 13:04:53 -04:00
DE1-SOC Documents Add publicly available documentation for DE1-SOC 2024-08-07 14:33:00 -04:00
lab1 Organise distributed files for lab1 2024-08-26 13:04:53 -04:00
.gitignore Add publicly available documentation for DE1-SOC 2024-08-07 14:33:00 -04:00
CPET561_lec_lab_syllabus_2231.pdf Init with information 2023-11-06 11:08:20 -05:00
lab2.pdf Init with information 2023-11-06 11:08:20 -05:00
lab3.pdf Init with information 2023-11-06 11:08:20 -05:00
lab4.pdf Init with information 2023-11-06 11:08:20 -05:00
lab5.pdf Init with information 2023-11-06 11:08:20 -05:00
lab6.pdf Init with information 2023-11-06 11:08:20 -05:00
lab7.pdf Init with information 2023-11-06 11:08:20 -05:00
LICENSE Initial commit 2023-11-06 10:59:00 -05:00
README.md Init with information 2023-11-06 11:08:20 -05:00

README.md

[CPET-561-01L1] - Embedded Systems Design 1

  • Time-block
  • Professor

Overview

Required Materials

  • Quartus 18.1
  • DE1-SOC development board Note that the DE1 is explicitly needed, as this course will use both the FPGA and SOC, and the DE0 board lacks the latter.

Required Foreknowledge

  • VHDL
  • Rudamentary C/C++
  • Quartus/ModelSim