3 KiB
2 cheatsheets, front-back, 8.5x11, handwritten
Both read and write code (assembly included)
NIOS Instructions do not count towards cheatsheet
TA in lab on reading day
Week1
|PC|Embedded|
|ASIC*|ASSP|SOP|SOPC*|FPGA*|CPLD|
IP core
soft cores v hard cores
SOF file: file for programming FPGA ELF file: Programming NIOS-II processor SOPCINFO file: Information about the FPGA config fed into Eclipse
Week 2
Assembly language
- Directional options (dest, source)
Instructions and classes
Example programs
How many registers?
How many values in a given register?
Week 3
|CISC|RISC|
NIOS-II Registers & Architecture
Compiler Optimisations (You don't want it)
Files and how they work together
Week 4
Scope vs visibility
Data types and type qualifiers
preprocessor directives
pointers
bitwise ops
C language
^: XOR; functionally, a bitwise inverter&: Bitwise AND&&: variable-wise AND (TRUE && FALSE) == FALSE
interrupts level v edge
Week 5
I/O devices
Pointer Offsets
| Address | Meaning | uint8 Offset |
uint16 Offset |
uint32 Offset |
|---|---|---|---|---|
0x11010 |
Data | 0 | 0 | 0 |
0x11014 |
Direction | 4 | 2 | 1 |
0x11018 |
Interrupt Mask | 8 | 4 | 2 |
0x11020 |
Edge capture | 12 | 6 | 3 |
PIO Access
Polling v Interrupts
ISR access - what to do in an ISR? (Interrupt Service Routine) Recognise an ISR call
Week 6
Signal Tap: Uses, advantages, disadvantages
Servos and PWM
Week 7
Memory
Organisation
what is it made of
access memory
address bits you need to index into a particular memory?
how many bytes exist in 1k x 16bit
types of memory?
RAM vs ROM
SRAM vs DRAM
Week 8
Address decoding
Big-endian vs little-endian
byte-addressable RAM
cache & hierarchy
locality
cache mapping - direct vs set associative
cache hits vs cache misses
- compulsory, etc
cache thrashing
cache replacement policies
Week 9
+/- of hardware accel
single v multithread
speed up analysis
custom instruction:
- where do they exist
- how many can you have
- different types and support
Custom components don't exist in the processor. Instructions are in the execute stage of the processor
Week 10
Audio concepts:
- nyquist
- aliasing
- sampling
- resolution
Pipelining
- max frequency increase by pipelining
- how is it in processor?
- difference between throughput, latency, and instruction time
- pipeline hazards
- branch prediction and impacts
- processor stages
Week 11
Static timing analysis
- synoptics is good for space
- timequest
- max frequency of synchronous system?
- netlist?
- setup & hold times?
- modeling timing
- longest and shortest path calc
- clock jitter vs clock skew
Week 12
Bus structure
basic wires for a bus
example of control signals
async vs synch
bus terminology
- bw vs effective bw
DMA/DMAC
- what does it do, how is it configured
- what info does the processor provide
- +/-
- bus arbitration schema
Week 13
Clock domain crossing single-bit vs bus crossing fast -> slow vs slow -> fast
Week 14
N/A
Week 15
Buffers, FIFO, Dual Port RAM (DPRAM)