icefunVHDL/encryptionKeyGenerator
2024-10-30 10:03:03 -04:00
..
counter.vhd Start encryption key generator side project 2024-10-25 21:15:38 -04:00
dff.vhd Start encryption key generator side project 2024-10-25 21:15:38 -04:00
dsdFinalLab.pdf Start encryption key generator side project 2024-10-25 21:15:38 -04:00
fsm.vhd Start encryption key generator side project 2024-10-25 21:15:38 -04:00
Makefile Add timing analysis to makefiles 2024-10-30 10:03:03 -04:00
README.md Start encryption key generator side project 2024-10-25 21:15:38 -04:00
rng.vhd Start encryption key generator side project 2024-10-25 21:15:38 -04:00
shiftRegister.vhd Start encryption key generator side project 2024-10-25 21:15:38 -04:00
toplevel.vhd Start encryption key generator side project 2024-10-25 21:15:38 -04:00

Encryption Key Generator

This is a project loosely based on RIT ECET department's Digital Systems Design class' final (optional) lab assignment, whose original description is in this repository as a pdf. The following modifications have been made:

  • For initial design purposes, the seed value will be hardcoded.
  • For easy debugging by an end user, the encryption key will also be displayed to the LED matrix to the iceFUN LED matrix.