Game server backend and API for PokéRogue
Updated 2025-04-27 12:03:34 -04:00
Updated 2025-04-21 19:30:20 -04:00
Milk-V Jupiter USB Gadget codebase; forked from IdeasOnBoard.org
Updated 2025-04-17 04:54:00 -04:00
Milk-V Jupiter Buildroot tooling
Updated 2025-04-17 04:54:00 -04:00
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
Updated 2025-04-10 08:06:34 -04:00
Updated 2025-04-07 22:58:15 -04:00
Documentation of my journey building a RISC-V computer with an NVidia GPU
Updated 2025-03-19 16:11:53 -04:00
Collection of Github Gist docs for SPL/FSBL/DRAM init information
Updated 2025-03-14 15:00:25 -04:00
Docker image for the Pleroma federated social network
Updated 2025-03-10 05:17:51 -04:00
Updated 2025-03-09 16:51:16 -04:00
Updated 2025-03-06 14:55:37 -05:00
This is the latest version of the internal repository from Pebble Technology providing the software to run on Pebble watches. Proprietary source code has been removed from this repository and it will not compile as-is. This is for information only.
Updated 2025-02-25 14:02:51 -05:00
An attempt at implementing a RISC-V 32-bit processor core
Updated 2025-02-06 10:09:15 -05:00
Nintendo Switch emulator
Updated 2025-02-06 09:52:53 -05:00
Config files, boiled down from Ohmyzsh, Ohmytmux, and other package managers
Updated 2025-01-22 20:41:43 -05:00
Milk-V Jupiter RISC-V Kernel Full History
Updated 2025-01-20 00:55:51 -05:00
Current submissions for Exercism's C track
Updated 2025-01-11 20:01:24 -05:00