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Colin Riley 2020-05-17 23:50:59 +01:00
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README.md
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# RPU
Basic RISC-V CPU implementation in VHDL.
This is a RV32I ISA CPU implementation, based off of my TPU CPU design. It is very simple, is missing several features, but can run rv32i-compiled GCC toolchain binaries at over 200MHz on a Digilent Arty S7-50 board, built with Xilinx Spartan 7 tools.
This is a RV32I ISA CPU implementation, based off of my TPU CPU design. It is very simple, is missing several features, but can run rv32i-compiled GCC toolchain binaries at over 200MHz on a Digilent Arty S7-50 board, built with Xilinx Spartan 7 tools. Can also boot Zephyr given correct SoC environment and invalid emulation handling of multiply/divide/mod M-extension instruction via invalid instruction trap.
Please let me know if you are using any of the RPU design in your own projects! I am contactable on twitter @domipheus.
# Implementation
Diagram does not include recently added CSR unit.
Diagram does not include recently added CSR & LINT units, or the fact that interrupts are supported.
![RPU Core overview](https://raw.githubusercontent.com/Domipheus/RPU/master/rpu_core_diagram.png)
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The tests in the repo are incredibly old and basic, and included only as a baseline to help. They will be expanded upon in time. The core_tb should work for basic simulator use and could be expanded for more complex debugging.
Currently working on: CSRs, Interrupts
Currently working on: Privilege modes, memory system overhaul, mmu support