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Basic RISC-V CPU implementation in VHDL.
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Colin Riley 47a0058836 Update readme to reflect latest status
2020-05-17 23:50:59 +01:00
tests Basic core execution simulator testbench. No memory subsystem, so will only execute from fixed array of instructions - but easy to use in the sim. 2018-11-16 22:43:47 +00:00
vhdl Core can now boot Zephyr RTOS 2020-05-17 23:39:17 +01:00
LICENSE Add License 2018-09-17 23:24:42 +01:00
README.md Update readme to reflect latest status 2020-05-17 23:50:59 +01:00
rpu_core_diagram.png Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing. 2018-09-11 23:53:41 +01:00

README.md

RPU

Basic RISC-V CPU implementation in VHDL.

This is a RV32I ISA CPU implementation, based off of my TPU CPU design. It is very simple, is missing several features, but can run rv32i-compiled GCC toolchain binaries at over 200MHz on a Digilent Arty S7-50 board, built with Xilinx Spartan 7 tools. Can also boot Zephyr given correct SoC environment and invalid emulation handling of multiply/divide/mod M-extension instruction via invalid instruction trap.

Please let me know if you are using any of the RPU design in your own projects! I am contactable on twitter @domipheus.

Implementation

Diagram does not include recently added CSR & LINT units, or the fact that interrupts are supported.

RPU Core overview

Implementation detail is written about via blogs available at http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-15-introducing-rpu/

The tests in the repo are incredibly old and basic, and included only as a baseline to help. They will be expanded upon in time. The core_tb should work for basic simulator use and could be expanded for more complex debugging.

Currently working on: Privilege modes, memory system overhaul, mmu support