Merge branch 'master' of https://github.com/lcbcFoo/riscv-leon

README.md

@@ -17,14 +17,14 @@ This is the ReonV project repository. ReonV is a modified version of the [Leon3]
 ## <a name="reonv"></a> The ReonV
 ### <a name="what-reonv"></a> What is ReonV?
 Simply speaking, ReonV is a RV32I version of the [Leon3](http://www.gaisler.com/index.php/products/processors/leon3) processor which is provided as part of the [GRLIB IP Library](http://www.gaisler.com/index.php/products/ipcores/soclibrary) on GPL license by [Cobham Gaisler AB](http://www.gaisler.com/).
-ReonV changed the Leon3 7-stage integer pipeline from SPARC to RISC-V, mantaining all other IP cores and resources provided by GRLIB IP Library untouched. With this, we aimed to provide all the support to synthesis and peripherals Leon3 has to a RISC-V processor.
+ReonV changed the Leon3 7-stage integer pipeline from SPARC to RISC-V, maintaining all other IP cores and resources provided by GRLIB IP Library untouched. With this, we aimed to provide all the support to synthesis and peripherals Leon3 has to a RISC-V processor.
 ### <a name="why-reonv"></a> Why creating a new RISC-V project?
 While there are good examples of advanced RISC-V projects, most of them built an entirely new processor and so had to build from the ground all the support to synthesis and peripherals to run it and also deal with compatibility problems when expanding the project to other environments. ReonV took another path. We used a very well documented, GPL licensed and tested IP Library, the GRLIB, made for the SPARC based Leon3 processor and changed its ISA to RISC-V, resulting in a RISC-V processor with support to many peripherals, different synthesis, simulation tools and FPGAs.
 Also, we wanted to show to the hardware developers community that it is possible to reuse hardware and that doing so makes development easier. 
 
 ---
 ## <a name="repo-map"></a> Repository Map
-The directories `bin`, `boards` and `software` where simply copied from GRLIB and contain scripts, templates and small programs used by GRLIB. The directory `doc` constains the documentation from GRLIB (may be updated with ReonV specific documentation on future). Directory `designs` contains all scripts and configuration designs for each specific FPGA board supported by Leon3 (and by ReonV). Directory `lib` constains the source code of the processor and of all peripherals or IP cores provided by GRLIB, the 7-stage integer pipeline changed to RISC-V is at `lib/gaisler/leon3v3/iu3.vhd`. Lastly, `riscv` contains scripts and configuration files to run a test example on ReonV (check [Running an Example](#running) section). 
+The directories `bin`, `boards` and `software` where simply copied from GRLIB and contain scripts, templates and small programs used by GRLIB. The directory `doc` constains the documentation from GRLIB (may be updated with ReonV specific documentation on future). Directory `designs` contains all scripts and configuration designs for each specific FPGA board supported by Leon3 (and by ReonV). Directory `lib` constains the source code of the processor and of all peripherals or IP cores provided by GRLIB, the 7-stage integer pipeline changed to RISC-V is at `lib/gaisler/leon3v3/iu3.vhd`. Lastly, `riscv` contains scripts and configuration files to run a test example on ReonV (check [Running an Example](#running) section). The original Leon3 SPARC `iu3.vhd` is at `riscv/tools` and can be used as a guide to future changes inside ReonV pipeline. 
 
 ---
 ## <a name="install"></a> Installation

riscv/README.md

@@ -5,7 +5,7 @@ changing a few commands to the ones your board requires.
 
 ---
 ## Overview
-* ReonV currentily implements RV32I without privilegied instructions, so it is important to use a compiler to this ISA (follow instructions on the main README). 
+* ReonV currently implements RV32I without privileged instructions, so it is important to use a compiler to this ISA (follow instructions on the main README). 
 * We will use GRMON2 to load, run and debug the program, since the processor DSU was not changed and it communicates with GRMON. However, GRMON2 was not designed for RISC-V and we have to take some workarounds to run a RISC-V program using it (more information on issue [GRMON2 and RISCV](https://github.com/lcbcFoo/ReonV/issues/5))
 * The design directory for this board is `designs/leon3-digilent-nexys4ddr`. If you are running on other board, you must use its own design directory.
 
@@ -133,7 +133,7 @@ grmon2> disassemble 0x44000000                           # Disassemble our outpu
 ## Important information (READ IT)
 * As described in the [GRMON2 and RISCV](https://github.com/lcbcFoo/ReonV/issues/5) issue, GRMON2 assumes processor is using big endian, therefore it shows bytes of a word backwards, for example:
 Number 974169 in RISC-V convention is `0x 00 0E DD 59`, GRMON2 shows it as `0x 59 DD 0E 00`
-This is an inconvenience that must be kept in mind when reading values from memory while using GRMON2 (especially if you use `dump` and try to compare with other results!).
+This is a visual inconvenience that must be kept in mind when reading values from memory while using GRMON2.
 * There is no console yet, you can check the results of your program with the simple `write`, `read` and `lseek` functions implemented at `posix.c`. They use memory section `0x44000000 - 0x450000000` as an output section, allowing you to `dump` this region with GRMON2 and compare result with another environment if you wish. 
 * The default value for stack is `0x43FFFFF0` and `0x43000000` for the heap.
 * Some commands of GRMON2 are `reg` and `reg w7` to see registers, set a breakpoint with `bp <address>`, run step by step with `step`, disassemble memory with `disassemble <memory address>` and a lot of others commands described on GRMON2´s [manual](http://www.gaisler.com/doc/grmon2.pdf).