mirror of
https://github.com/lcbcFoo/ReonV.git
synced 2025-04-18 18:44:43 -04:00
Printed string
This commit is contained in:
parent
0adc8f6131
commit
be0d492e0b
9 changed files with 168 additions and 51 deletions
|
@ -141,7 +141,6 @@ CONFIG_ICACHE_ALGORND=y
|
||||||
# CONFIG_ICACHE_ALGOLRR is not set
|
# CONFIG_ICACHE_ALGOLRR is not set
|
||||||
# CONFIG_ICACHE_ALGOLRU is not set
|
# CONFIG_ICACHE_ALGOLRU is not set
|
||||||
# CONFIG_ICACHE_LOCK is not set
|
# CONFIG_ICACHE_LOCK is not set
|
||||||
# CONFIG_ICACHE_LRAM is not set
|
|
||||||
CONFIG_DCACHE_ENABLE=y
|
CONFIG_DCACHE_ENABLE=y
|
||||||
# CONFIG_DCACHE_ASSO1 is not set
|
# CONFIG_DCACHE_ASSO1 is not set
|
||||||
# CONFIG_DCACHE_ASSO2 is not set
|
# CONFIG_DCACHE_ASSO2 is not set
|
||||||
|
@ -165,12 +164,26 @@ CONFIG_DCACHE_ALGORND=y
|
||||||
# CONFIG_DCACHE_LOCK is not set
|
# CONFIG_DCACHE_LOCK is not set
|
||||||
# CONFIG_DCACHE_SNOOP is not set
|
# CONFIG_DCACHE_SNOOP is not set
|
||||||
CONFIG_CACHE_FIXED=0
|
CONFIG_CACHE_FIXED=0
|
||||||
# CONFIG_DCACHE_LRAM is not set
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# MMU
|
# MMU
|
||||||
#
|
#
|
||||||
# CONFIG_MMU_ENABLE is not set
|
CONFIG_MMU_ENABLE=y
|
||||||
|
CONFIG_MMU_COMBINED=y
|
||||||
|
# CONFIG_MMU_SPLIT is not set
|
||||||
|
# CONFIG_MMU_REPARRAY is not set
|
||||||
|
CONFIG_MMU_REPINCREMENT=y
|
||||||
|
# CONFIG_MMU_I2 is not set
|
||||||
|
# CONFIG_MMU_I4 is not set
|
||||||
|
CONFIG_MMU_I8=y
|
||||||
|
# CONFIG_MMU_I16 is not set
|
||||||
|
# CONFIG_MMU_I32 is not set
|
||||||
|
# CONFIG_MMU_I64 is not set
|
||||||
|
CONFIG_MMU_PAGE_4K=y
|
||||||
|
# CONFIG_MMU_PAGE_8K is not set
|
||||||
|
# CONFIG_MMU_PAGE_16K is not set
|
||||||
|
# CONFIG_MMU_PAGE_32K is not set
|
||||||
|
# CONFIG_MMU_PAGE_PROG is not set
|
||||||
|
|
||||||
#
|
#
|
||||||
# Debug Support Unit
|
# Debug Support Unit
|
||||||
|
@ -183,14 +196,7 @@ CONFIG_DSU_ITRACESZ1=y
|
||||||
# CONFIG_DSU_ITRACESZ8 is not set
|
# CONFIG_DSU_ITRACESZ8 is not set
|
||||||
# CONFIG_DSU_ITRACESZ16 is not set
|
# CONFIG_DSU_ITRACESZ16 is not set
|
||||||
# CONFIG_DSU_ITRACE_2P is not set
|
# CONFIG_DSU_ITRACE_2P is not set
|
||||||
CONFIG_DSU_ATRACE=y
|
# CONFIG_DSU_ATRACE is not set
|
||||||
CONFIG_DSU_ATRACESZ1=y
|
|
||||||
# CONFIG_DSU_ATRACESZ2 is not set
|
|
||||||
# CONFIG_DSU_ATRACESZ4 is not set
|
|
||||||
# CONFIG_DSU_ATRACESZ8 is not set
|
|
||||||
# CONFIG_DSU_ATRACESZ16 is not set
|
|
||||||
# CONFIG_DSU_AFILT is not set
|
|
||||||
# CONFIG_DSU_ASTAT is not set
|
|
||||||
# CONFIG_STAT_ENABLE is not set
|
# CONFIG_STAT_ENABLE is not set
|
||||||
|
|
||||||
#
|
#
|
||||||
|
@ -299,15 +305,8 @@ CONFIG_UA1_FIFO2=y
|
||||||
# CONFIG_UA1_FIFO8 is not set
|
# CONFIG_UA1_FIFO8 is not set
|
||||||
# CONFIG_UA1_FIFO16 is not set
|
# CONFIG_UA1_FIFO16 is not set
|
||||||
# CONFIG_UA1_FIFO32 is not set
|
# CONFIG_UA1_FIFO32 is not set
|
||||||
CONFIG_IRQ3_ENABLE=y
|
# CONFIG_IRQ3_ENABLE is not set
|
||||||
# CONFIG_IRQ3_SEC is not set
|
# CONFIG_GPT_ENABLE is not set
|
||||||
CONFIG_GPT_ENABLE=y
|
|
||||||
CONFIG_GPT_NTIM=2
|
|
||||||
CONFIG_GPT_SW=8
|
|
||||||
CONFIG_GPT_TW=32
|
|
||||||
CONFIG_GPT_IRQ=8
|
|
||||||
CONFIG_GPT_SEPIRQ=y
|
|
||||||
# CONFIG_GPT_WDOGEN is not set
|
|
||||||
CONFIG_GRGPIO_ENABLE=y
|
CONFIG_GRGPIO_ENABLE=y
|
||||||
CONFIG_GRGPIO_WIDTH=8
|
CONFIG_GRGPIO_WIDTH=8
|
||||||
CONFIG_GRGPIO_IMASK=0000
|
CONFIG_GRGPIO_IMASK=0000
|
||||||
|
|
|
@ -136,7 +136,6 @@
|
||||||
#undef CONFIG_ICACHE_ALGOLRR
|
#undef CONFIG_ICACHE_ALGOLRR
|
||||||
#undef CONFIG_ICACHE_ALGOLRU
|
#undef CONFIG_ICACHE_ALGOLRU
|
||||||
#undef CONFIG_ICACHE_LOCK
|
#undef CONFIG_ICACHE_LOCK
|
||||||
#undef CONFIG_ICACHE_LRAM
|
|
||||||
#define CONFIG_DCACHE_ENABLE 1
|
#define CONFIG_DCACHE_ENABLE 1
|
||||||
#undef CONFIG_DCACHE_ASSO1
|
#undef CONFIG_DCACHE_ASSO1
|
||||||
#undef CONFIG_DCACHE_ASSO2
|
#undef CONFIG_DCACHE_ASSO2
|
||||||
|
@ -160,11 +159,25 @@
|
||||||
#undef CONFIG_DCACHE_LOCK
|
#undef CONFIG_DCACHE_LOCK
|
||||||
#undef CONFIG_DCACHE_SNOOP
|
#undef CONFIG_DCACHE_SNOOP
|
||||||
#define CONFIG_CACHE_FIXED 0
|
#define CONFIG_CACHE_FIXED 0
|
||||||
#undef CONFIG_DCACHE_LRAM
|
|
||||||
/*
|
/*
|
||||||
* MMU
|
* MMU
|
||||||
*/
|
*/
|
||||||
#undef CONFIG_MMU_ENABLE
|
#define CONFIG_MMU_ENABLE 1
|
||||||
|
#define CONFIG_MMU_COMBINED 1
|
||||||
|
#undef CONFIG_MMU_SPLIT
|
||||||
|
#undef CONFIG_MMU_REPARRAY
|
||||||
|
#define CONFIG_MMU_REPINCREMENT 1
|
||||||
|
#undef CONFIG_MMU_I2
|
||||||
|
#undef CONFIG_MMU_I4
|
||||||
|
#define CONFIG_MMU_I8 1
|
||||||
|
#undef CONFIG_MMU_I16
|
||||||
|
#undef CONFIG_MMU_I32
|
||||||
|
#undef CONFIG_MMU_I64
|
||||||
|
#define CONFIG_MMU_PAGE_4K 1
|
||||||
|
#undef CONFIG_MMU_PAGE_8K
|
||||||
|
#undef CONFIG_MMU_PAGE_16K
|
||||||
|
#undef CONFIG_MMU_PAGE_32K
|
||||||
|
#undef CONFIG_MMU_PAGE_PROG
|
||||||
/*
|
/*
|
||||||
* Debug Support Unit
|
* Debug Support Unit
|
||||||
*/
|
*/
|
||||||
|
@ -176,14 +189,7 @@
|
||||||
#undef CONFIG_DSU_ITRACESZ8
|
#undef CONFIG_DSU_ITRACESZ8
|
||||||
#undef CONFIG_DSU_ITRACESZ16
|
#undef CONFIG_DSU_ITRACESZ16
|
||||||
#undef CONFIG_DSU_ITRACE_2P
|
#undef CONFIG_DSU_ITRACE_2P
|
||||||
#define CONFIG_DSU_ATRACE 1
|
#undef CONFIG_DSU_ATRACE
|
||||||
#define CONFIG_DSU_ATRACESZ1 1
|
|
||||||
#undef CONFIG_DSU_ATRACESZ2
|
|
||||||
#undef CONFIG_DSU_ATRACESZ4
|
|
||||||
#undef CONFIG_DSU_ATRACESZ8
|
|
||||||
#undef CONFIG_DSU_ATRACESZ16
|
|
||||||
#undef CONFIG_DSU_AFILT
|
|
||||||
#undef CONFIG_DSU_ASTAT
|
|
||||||
#undef CONFIG_STAT_ENABLE
|
#undef CONFIG_STAT_ENABLE
|
||||||
/*
|
/*
|
||||||
* Fault-tolerance
|
* Fault-tolerance
|
||||||
|
@ -281,15 +287,8 @@
|
||||||
#undef CONFIG_UA1_FIFO8
|
#undef CONFIG_UA1_FIFO8
|
||||||
#undef CONFIG_UA1_FIFO16
|
#undef CONFIG_UA1_FIFO16
|
||||||
#undef CONFIG_UA1_FIFO32
|
#undef CONFIG_UA1_FIFO32
|
||||||
#define CONFIG_IRQ3_ENABLE 1
|
#undef CONFIG_IRQ3_ENABLE
|
||||||
#undef CONFIG_IRQ3_SEC
|
#undef CONFIG_GPT_ENABLE
|
||||||
#define CONFIG_GPT_ENABLE 1
|
|
||||||
#define CONFIG_GPT_NTIM (2)
|
|
||||||
#define CONFIG_GPT_SW (8)
|
|
||||||
#define CONFIG_GPT_TW (32)
|
|
||||||
#define CONFIG_GPT_IRQ (8)
|
|
||||||
#define CONFIG_GPT_SEPIRQ 1
|
|
||||||
#undef CONFIG_GPT_WDOGEN
|
|
||||||
#define CONFIG_GRGPIO_ENABLE 1
|
#define CONFIG_GRGPIO_ENABLE 1
|
||||||
#define CONFIG_GRGPIO_WIDTH (8)
|
#define CONFIG_GRGPIO_WIDTH (8)
|
||||||
#define CONFIG_GRGPIO_IMASK 0000
|
#define CONFIG_GRGPIO_IMASK 0000
|
||||||
|
|
|
@ -57,15 +57,15 @@ package config is
|
||||||
constant CFG_DLRAMEN : integer := 0;
|
constant CFG_DLRAMEN : integer := 0;
|
||||||
constant CFG_DLRAMADDR: integer := 16#8F#;
|
constant CFG_DLRAMADDR: integer := 16#8F#;
|
||||||
constant CFG_DLRAMSZ : integer := 1;
|
constant CFG_DLRAMSZ : integer := 1;
|
||||||
constant CFG_MMUEN : integer := 0;
|
constant CFG_MMUEN : integer := 1;
|
||||||
constant CFG_ITLBNUM : integer := 2;
|
constant CFG_ITLBNUM : integer := 8;
|
||||||
constant CFG_DTLBNUM : integer := 2;
|
constant CFG_DTLBNUM : integer := 2;
|
||||||
constant CFG_TLB_TYPE : integer := 1 + 0*2;
|
constant CFG_TLB_TYPE : integer := 1 + 0*2;
|
||||||
constant CFG_TLB_REP : integer := 1;
|
constant CFG_TLB_REP : integer := 1;
|
||||||
constant CFG_MMU_PAGE : integer := 0;
|
constant CFG_MMU_PAGE : integer := 0;
|
||||||
constant CFG_DSU : integer := 1;
|
constant CFG_DSU : integer := 1;
|
||||||
constant CFG_ITBSZ : integer := 1 + 64*0;
|
constant CFG_ITBSZ : integer := 1 + 64*0;
|
||||||
constant CFG_ATBSZ : integer := 1;
|
constant CFG_ATBSZ : integer := 0;
|
||||||
constant CFG_AHBPF : integer := 0;
|
constant CFG_AHBPF : integer := 0;
|
||||||
constant CFG_LEON3FT_EN : integer := 0;
|
constant CFG_LEON3FT_EN : integer := 0;
|
||||||
constant CFG_IUFT_EN : integer := 0;
|
constant CFG_IUFT_EN : integer := 0;
|
||||||
|
@ -147,15 +147,15 @@ package config is
|
||||||
constant CFG_UART1_ENABLE : integer := 1;
|
constant CFG_UART1_ENABLE : integer := 1;
|
||||||
constant CFG_UART1_FIFO : integer := 2;
|
constant CFG_UART1_FIFO : integer := 2;
|
||||||
-- LEON3 interrupt controller
|
-- LEON3 interrupt controller
|
||||||
constant CFG_IRQ3_ENABLE : integer := 1;
|
constant CFG_IRQ3_ENABLE : integer := 0;
|
||||||
constant CFG_IRQ3_NSEC : integer := 0;
|
constant CFG_IRQ3_NSEC : integer := 0;
|
||||||
-- Modular timer
|
-- Modular timer
|
||||||
constant CFG_GPT_ENABLE : integer := 1;
|
constant CFG_GPT_ENABLE : integer := 0;
|
||||||
constant CFG_GPT_NTIM : integer := (2);
|
constant CFG_GPT_NTIM : integer := 1;
|
||||||
constant CFG_GPT_SW : integer := (8);
|
constant CFG_GPT_SW : integer := 8;
|
||||||
constant CFG_GPT_TW : integer := (32);
|
constant CFG_GPT_TW : integer := 8;
|
||||||
constant CFG_GPT_IRQ : integer := (8);
|
constant CFG_GPT_IRQ : integer := 8;
|
||||||
constant CFG_GPT_SEPIRQ : integer := 1;
|
constant CFG_GPT_SEPIRQ : integer := 0;
|
||||||
constant CFG_GPT_WDOGEN : integer := 0;
|
constant CFG_GPT_WDOGEN : integer := 0;
|
||||||
constant CFG_GPT_WDOG : integer := 16#0#;
|
constant CFG_GPT_WDOG : integer := 16#0#;
|
||||||
-- GPIO port
|
-- GPIO port
|
||||||
|
|
|
@ -29,6 +29,8 @@ int main(){
|
||||||
|
|
||||||
// Writes the check into output memory section
|
// Writes the check into output memory section
|
||||||
write(0, &correct, sizeof(int));
|
write(0, &correct, sizeof(int));
|
||||||
|
|
||||||
|
dbgleon_printf("CARAI PRINT");
|
||||||
}
|
}
|
||||||
|
|
||||||
int fib(int i){
|
int fib(int i){
|
||||||
|
|
BIN
riscv/main.out
Executable file
BIN
riscv/main.out
Executable file
Binary file not shown.
|
@ -1,4 +1,4 @@
|
||||||
/*
|
/*
|
||||||
* This file is part of the ReonV distribution (https://github.com/lcbcFoo/ReonV).
|
* This file is part of the ReonV distribution (https://github.com/lcbcFoo/ReonV).
|
||||||
* Copyright (c) 2018 to Lucas C. B. Castro.
|
* Copyright (c) 2018 to Lucas C. B. Castro.
|
||||||
*
|
*
|
||||||
|
@ -28,6 +28,85 @@ static char* heap = (char*) HEAP_START;
|
||||||
static char* out_mem = (char*)OUT_MEM_BEGIN;
|
static char* out_mem = (char*)OUT_MEM_BEGIN;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The following defines the bits in the LEON UART Status Registers.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */
|
||||||
|
#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
|
||||||
|
#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
|
||||||
|
#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */
|
||||||
|
#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */
|
||||||
|
#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */
|
||||||
|
#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
|
||||||
|
#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The following defines the bits in the LEON UART Status Registers.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */
|
||||||
|
#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */
|
||||||
|
#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */
|
||||||
|
#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */
|
||||||
|
#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */
|
||||||
|
#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */
|
||||||
|
#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */
|
||||||
|
#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
volatile unsigned int data;
|
||||||
|
volatile unsigned int status;
|
||||||
|
volatile unsigned int ctrl;
|
||||||
|
volatile unsigned int scaler;
|
||||||
|
} LEON23_APBUART_Regs_Map;
|
||||||
|
|
||||||
|
|
||||||
|
#define UART_TIMEOUT 100000
|
||||||
|
static LEON23_APBUART_Regs_Map *uart_regs = 0;
|
||||||
|
//int *console = (int *) 0x80000100;
|
||||||
|
int
|
||||||
|
dbgleon_printf (const char *fmt, ...)
|
||||||
|
{
|
||||||
|
unsigned int i, loops, ch;
|
||||||
|
int printed_len;
|
||||||
|
char printk_buf[1024];
|
||||||
|
char *p = printk_buf;
|
||||||
|
|
||||||
|
/* Emit the output into the temporary buffer */
|
||||||
|
p = fmt;
|
||||||
|
printed_len = 10;
|
||||||
|
|
||||||
|
uart_regs = (LEON23_APBUART_Regs_Map*) 0x80000100;
|
||||||
|
if (uart_regs){
|
||||||
|
while (printed_len-- != 0){
|
||||||
|
ch = *p++;
|
||||||
|
if (uart_regs){
|
||||||
|
loops = 0;
|
||||||
|
|
||||||
|
while (!(uart_regs->status & LEON_REG_UART_STATUS_THE) && (loops < UART_TIMEOUT))
|
||||||
|
loops++;
|
||||||
|
|
||||||
|
uart_regs->data = ch;
|
||||||
|
loops = 0;
|
||||||
|
while (!(uart_regs->status & LEON_REG_UART_STATUS_TSE) && (loops < UART_TIMEOUT))
|
||||||
|
loops++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
//---------------------
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
// Exit application
|
// Exit application
|
||||||
void _exit_c( int status ) {
|
void _exit_c( int status ) {
|
||||||
__asm("ebreak");
|
__asm("ebreak");
|
||||||
|
|
BIN
riscv/posix.o
Normal file
BIN
riscv/posix.o
Normal file
Binary file not shown.
BIN
riscv/reonv_crt0.o
Normal file
BIN
riscv/reonv_crt0.o
Normal file
Binary file not shown.
38
riscv/teste_uart.c
Normal file
38
riscv/teste_uart.c
Normal file
|
@ -0,0 +1,38 @@
|
||||||
|
int fib();
|
||||||
|
#include <stdio.h>
|
||||||
|
|
||||||
|
int main(){
|
||||||
|
int n = 8;
|
||||||
|
|
||||||
|
// Allocates memory for arrays
|
||||||
|
int* array = (int*)sbrk(n * sizeof(int));
|
||||||
|
int* array2 = (int*)sbrk(n * sizeof(int));
|
||||||
|
|
||||||
|
// Calculates fib(i), 1 <= i <= n
|
||||||
|
for(int i = 1; i <= n; i++)
|
||||||
|
array[i-1] = fib(i);
|
||||||
|
|
||||||
|
// Writes results on output memory section
|
||||||
|
write(0, array,n * sizeof(int));
|
||||||
|
|
||||||
|
// Sets pointer to beginning of output memory section
|
||||||
|
lseek(0, -n*sizeof(int), SEEK_CUR);
|
||||||
|
|
||||||
|
// Reads the results into array2
|
||||||
|
read(0, array2, n * sizeof(int));
|
||||||
|
|
||||||
|
// Checks if they were copied correctly
|
||||||
|
int correct = 0xAAAAAAAA;
|
||||||
|
for(int i = 0; i < n; i++)
|
||||||
|
if(array[i] != array2[i])
|
||||||
|
correct = 0xBBBBBBBB;
|
||||||
|
|
||||||
|
// Writes the check into output memory section
|
||||||
|
write(0, &correct, sizeof(int));
|
||||||
|
}
|
||||||
|
|
||||||
|
int fib(int i){
|
||||||
|
if(i == 1 || i == 2)
|
||||||
|
return 1;
|
||||||
|
return fib(i-1) + fib(i-2);
|
||||||
|
}
|
Loading…
Add table
Reference in a new issue