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https://github.com/lcbcFoo/ReonV.git
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77 lines
3.8 KiB
VHDL
77 lines
3.8 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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-- Dummy sld_virtual_jtag - ModelSim crashes on default one
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entity sld_virtual_jtag is
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generic (
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lpm_type : string := "SLD_VIRTUAL_JTAG";
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-- required by coding standard
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lpm_hint : string := "SLD_VIRTUAL_JTAG"; -- required by coding standard
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sld_auto_instance_index : string := "NO";
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-- Yes of auto index is desired and no otherwise
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sld_instance_index : integer := 0;
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-- Index to be used if SLD_AUTO_INSTANCE_INDEX is no
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sld_ir_width : integer := 1;
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-- the width of the IR register
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sld_sim_n_scan : integer := 0;
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-- the number of scans in the simulation model
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sld_sim_total_length : integer := 0;
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-- the total bit width of all DR scan values
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sld_sim_action : string := "");
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-- the actions to be simulated in a format specified by the documentation
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port (
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tdo : in std_logic := '0'; -- tdo signal into megafunction
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ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
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-- parallel ir data into megafunction
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tck : out std_logic; -- tck signal from megafunction
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tdi : out std_logic; -- tdi signal from megafunction
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ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
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-- paraller ir data from megafunction
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virtual_state_cdr : out std_logic; -- cdr state signal of megafunction
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virtual_state_sdr : out std_logic; -- sdr state signal of megafunction
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virtual_state_e1dr : out std_logic;
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-- e1dr state signal of megafunction
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virtual_state_pdr : out std_logic; -- pdr state signal of megafunction
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virtual_state_e2dr : out std_logic;
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-- e2dr state signal of megafunction
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virtual_state_udr : out std_logic; -- udr state signal of megafunction
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virtual_state_cir : out std_logic; -- cir state signal of megafunction
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virtual_state_uir : out std_logic; -- uir state signal of megafunction
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jtag_state_tlr : out std_logic; -- Test, Logic, Reset state
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jtag_state_rti : out std_logic; -- Run, Test, Idle state
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jtag_state_sdrs : out std_logic; -- Select DR scan state
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jtag_state_cdr : out std_logic; -- capture DR state
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jtag_state_sdr : out std_logic; -- Shift DR state
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jtag_state_e1dr : out std_logic; -- exit 1 dr state
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jtag_state_pdr : out std_logic; -- pause dr state
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jtag_state_e2dr : out std_logic; -- exit 2 dr state
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jtag_state_udr : out std_logic; -- update dr state
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jtag_state_sirs : out std_logic; -- Select IR scan state
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jtag_state_cir : out std_logic; -- capture IR state
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jtag_state_sir : out std_logic; -- shift IR state
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jtag_state_e1ir : out std_logic; -- exit 1 IR state
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jtag_state_pir : out std_logic; -- pause IR state
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jtag_state_e2ir : out std_logic; -- exit 2 IR state
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jtag_state_uir : out std_logic; -- update IR state
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tms : out std_logic); -- tms signal
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end sld_virtual_jtag;
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architecture structural of sld_virtual_jtag is
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begin -- structural
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-- dummy drivers to avoid modelsim warnings
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tck <= '0';
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tdi <= '0';
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ir_in <= (others => '0');
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virtual_state_cdr <= '0';
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virtual_state_sdr <= '0';
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virtual_state_udr <= '0';
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end structural;
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