mirror of
https://github.com/lcbcFoo/ReonV.git
synced 2025-04-18 18:44:43 -04:00
99 lines
2.5 KiB
Tcl
99 lines
2.5 KiB
Tcl
set TOP_ldf_contents ""
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proc create_lattice_top_ldf {} {
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global TOP PART SPEED PACKAGE
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upvar TOP_ldf_contents tlc
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append tlc "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n"
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append tlc "<BaliProject version=\"1.3\" title=\"$TOP\" device=\"$PART$SPEED$PACKAGE\" default_implementation=\"$TOP\">\n"
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append tlc " <Options/>\n"
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append tlc " <Implementation title=\"$TOP\" dir=\"lattice\" description=\"$TOP\" default_strategy=\"Timing\">\n"
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append tlc " <Options/>\n"
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return
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}
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proc append_file_lattice_top_ldf {f finfo} {
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set i [dict get $finfo i]
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set bn [dict get $finfo bn]
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switch $i {
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"vhdlp1735" {
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return
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}
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"vhdlmtie" {
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return
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}
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"vhdlsynpe" {
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return
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}
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"vhdldce" {
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return
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}
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"vhdlcdse" {
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return
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}
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"vhdlxile" {
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return
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}
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"vhdlfpro" {
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return
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}
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"vhdlprec" {
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return
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}
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"vhdlsyn" {
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set q [dict get $finfo q]
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set l [dict get $finfo l]
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global XSYNPLIBSKIP XSYNPDIRSKIP SYNPSKIP TOP
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if {[lsearchmatch $XSYNPLIBSKIP $bn] < 0 && [lsearchmatch $XSYNPDIRSKIP $l] < 0 && [lsearchmatch $SYNPSKIP $q] < 0 } {
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upvar TOP_ldf_contents tlc
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append tlc " <Source name=\"$f\" type=\"VHDL\" type_short=\"VHDL\">\n"
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if {[string equal $bn "work"] && [string equal $l "local" ] } {
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append tlc " <Options/>\n"
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} else {
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append tlc " <Options lib=\"$bn\"/>\n"
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}
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append tlc " </Source>\n"
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}
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return
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}
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"vlogsyn" {
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return
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}
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"svlogsyn" {
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return
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}
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"vhdlsim" {
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set l [dict get $finfo l]
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if {[string equal $l "local"] && [string equal $bn "work"] } {
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} else {
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global TOP
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upvar TOP_ldf_contents tlc
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append tlc " <Source name=\"$f\" type=\"VHDL\" type_short=\"VHDL\" syn_sim=\"SimOnly\" excluded=\"TRUE\" >\n"
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append tlc " <Options lib=\"$bn\"/>\n"
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append tlc " </Source>\n"
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}
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return
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}
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"vlogsim" {
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return
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}
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"svlogsim" {
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return
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}
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}
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return
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}
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proc eof_lattice_top_ldf {} {
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global UCF SDCFILE TOP
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upvar TOP_ldf_contents tlc
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append tlc " <Source name=\"$UCF\" type=\"Logic Preference\" type_short=\"LPF\">\n"
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append tlc " <Options/>\n"
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append tlc " </Source>\n"
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append tlc " <Source name=\"$SDCFILE\" type=\"Synplify Design Constraints File\" type_short=\"SDC\">\n"
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append tlc " <Options/>\n"
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append tlc " </Source>\n"
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append tlc " </Implementation>\n"
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append tlc "</BaliProject>"
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set ldffile [open "$TOP.ldf" a]
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puts $ldffile $tlc
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close $ldffile
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}
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