mirror of
https://github.com/lcbcFoo/ReonV.git
synced 2025-04-18 18:44:43 -04:00
186 lines
6.3 KiB
Tcl
186 lines
6.3 KiB
Tcl
set planAhead_contents ""
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proc create_xlnx_planAhead {} {
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global TOP DESIGN DEVICE PLANAHEAD_SIMSET GRLIB_XIL_PlanAhead_Simulator SIMTOP PROTOBOARD
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upvar planAhead_contents pc
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file mkdir "planahead"
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append pc "# Xilinx planAhead script for LEON/GRLIB"
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append pc "\n# Create a new project"
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append pc "\ncreate_project $DESIGN ./planahead/$DESIGN -part $DEVICE -force"
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if {![string equal $PLANAHEAD_SIMSET "sim_1"]} {
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append pc "\ncreate_fileset -simset $PLANAHEAD_SIMSET"
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}
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append pc "\n# Board, part and design properties"
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append pc "\nset_property target_simulator $GRLIB_XIL_PlanAhead_Simulator \[current_project\]"
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append pc "\nset_property top_lib work \[current_fileset\]"
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append pc "\nset_property top_arch rtl \[current_fileset\]"
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append pc "\nset_property top $TOP \[current_fileset\]"
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append pc "\nset_property target_language VHDL \[current_project\]"
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if {![string equal $PROTOBOARD ""]} {
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append pc "\nset_property board $PROTOBOARD \[current_project\]"
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}
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append pc "\n# Use manual compile order"
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append pc "\n#set_property source_mgmt_mode DisplayOnly \[current_project\]"
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append pc "\n# Disable option: Include all design sources for simulation"
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append pc "\n#set_property SOURCE_SET \{\} \[get_filesets $PLANAHEAD_SIMSET\]"
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append pc "\n# Add files for simulation and synthesis"
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append pc "\nset_property top $SIMTOP \[get_filesets $PLANAHEAD_SIMSET\]"
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return
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}
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proc append_file_xlnx_planAhead {f finfo} {
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set i [dict get $finfo i]
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set bn [dict get $finfo bn]
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switch $i {
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"vhdlp1735" {
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return
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}
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"vhdlmtie" {
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return
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}
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"vhdlsynpe" {
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return
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}
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"vhdldce" {
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return
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}
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"vhdlcdse" {
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return
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}
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"vhdlxile" {
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global VIVADOVHDL
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upvar planAhead_contents pc
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append pc "\n$VIVADOVHDL $bn $f"
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append pc "\nset_property file_type VHDL \[get_files $f\]"
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return
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}
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"vhdlfpro" {
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return
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}
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"vhdlprec" {
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return
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}
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"vhdlsyn" {
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set l [dict get $finfo l]
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global VIVADOVHDL
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upvar planAhead_contents pc
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append pc "\n$VIVADOVHDL $bn $f"
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return
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}
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"vlogsyn" {
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set l [dict get $finfo l]
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global VIVADOVLOG
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upvar planAhead_contents pc
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append pc "\n$VIVADOVLOG $bn $f"
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append pc "\nset_property file_type Verilog \[get_files $f\]"
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return
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}
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"svlogsyn" {
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global VIVADOVLOG
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upvar planAhead_contents pc
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append pc "\n$VIVADOVLOG $bn -sv $f"
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return
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}
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"vhdlsim" {
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set l [dict get $finfo l]
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global VIVADOLIBSKIP VIVADODIRSKIP VIVADOSKIP PLANAHEAD_SIMSET
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upvar planAhead_contents pc
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set l [dict get $finfo l]
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set q [dict get $finfo q]
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if {[lsearchmatch $VIVADOLIBSKIP $bn] < 0 && [lsearchmatch $VIVADODIRSKIP $l] < 0 && [lsearchmatch $VIVADOSKIP $q] < 0 } {
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append pc "\nadd_files -fileset $PLANAHEAD_SIMSET -norecurse $f"
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append pc "\nset_property library $bn \[get_files $f\]"
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append pc "\nset_property file_type VHDL \[get_files $f\]"
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}
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return
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}
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"vlogsim" {
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set l [dict get $finfo l]
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global PLANAHEAD_SIMSET
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upvar planAhead_contents pc
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append pc "\nadd_files -fileset $PLANAHEAD_SIMSET -norecurse $f"
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append pc "\nset_property library $bn \[get_files $f\]"
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append pc "\nset_property file_type Verilog \[get_files $f\]"
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return
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}
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"svlogsim" {
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global PLANAHEAD_SIMSET
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upvar planAhead_contents pc
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append pc "\nadd_files -fileset $PLANAHEAD_SIMSET -norecurse $f"
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append pc "\nset_property library $bn \[get_files $f\]"
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return
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}
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}
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return
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}
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proc eof_xlnx_planAhead {} {
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global GRLIB NETLISTTECH PLANAHEAD_SIMSET GRLIB_XIL_PlanAhead_sim_verilog_define \
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UCF_PLANAHEAD PLANAHEAD_SYNTH_STRATEGY PLANAHEAD_IMPL_STRATEGY PLANAHEAD_BITGEN PROTOBOARD \
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CONFIG_MIG_DDR2 TOP
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upvar planAhead_contents pc
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append pc "\nadd_files -fileset $PLANAHEAD_SIMSET prom.srec ram.srec"
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if {![string equal $GRLIB_XIL_PlanAhead_sim_verilog_define ""]} {
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append pc "\nset_property verilog_define \{$GRLIB_XIL_PlanAhead_sim_verilog_define\} \[get_filesets $PLANAHEAD_SIMSET\]"
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}
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if {[file isdirectory $GRLIB/netlists/xilinx/$NETLISTTECH ]} {
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append pc "\nimport_files $GRLIB/netlists/xilinx/$NETLISTTECH"
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}
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if {[string equal $PROTOBOARD "zedBoard"]} {
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file mkdir "planahead/xps_files"
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file copy "./edk_files/leon3_zedboard" "planAhead/xps_files/"
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append pc "\n# Add Leon3 PS Zedboard Design"
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append pc "\nadd_files ./planahead/xps_files/leon3_zedboard/leon3_zedboard.xmp"
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append pc "\nmake_wrapper -files \[get_files ./planahead/xps_files/leon3_zedboard/leon3_zedboard.xmp\] -top -fileset \[get_filesets sources_1\] -import"
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append pc "\nupdate_compile_order -fileset sources_1"
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}
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append pc "\n# Read board specific constraints"
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foreach i $UCF_PLANAHEAD {
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if {[file exists $i]} {
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append pc "\nread_ucf $i"
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}
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}
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if {[string equal $CONFIG_MIG_DDR2 "y"]} {
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if {[file exists "mig/user_design/par/mig.ucf"]} {
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append pc "\nread_ucf mig/user_design/par/mig.ucf"
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}
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}
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# append pc "create_run synth_$(DESIGN) -flow {$(PLANAHEAD_SYNTH_FLOW)} -strategy {$(PLANAHEAD_SYNTH_STRATEGY)}"
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append pc "\nset_property steps.xst.args.netlist_hierarchy as_optimized \[get_runs synth_1\]"
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append pc "\nset_property strategy $PLANAHEAD_SYNTH_STRATEGY \[get_runs synth_1\]"
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set phfile [open "planahead/$TOP\_planAhead.tcl" w]
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puts $phfile $pc
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close $phfile
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set pc "# Elaborate design to be able to apply SDC to top level"
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append pc "\nlaunch_runs -jobs 1 synth_1"
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append pc "\nwait_on_run -timeout 120 synth_1"
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append pc "\n# Launch place and route"
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append pc "\nset_property strategy $PLANAHEAD_IMPL_STRATEGY \[get_runs impl_1\]"
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append pc "\n#set_property steps.map.args.mt on \[get_runs impl_1\]"
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append pc "\n#set_property steps.par.args.mt 4 \[get_runs impl_1\]"
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append pc "\nset_property steps.bitgen.args.m true \[get_runs impl_1\]"
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if {![string equal $PLANAHEAD_BITGEN ""]} {
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append pc "\nset_property {steps.bitgen.args.More Options} \{ $PLANAHEAD_BITGEN \} \[get_runs impl_1\]"
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}
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append pc "\nlaunch_runs -jobs 1 impl_1 -to_step Bitgen"
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append pc "\nwait_on_run -timeout 120 impl_1"
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if {[string equal $PROTOBOARD "zedBoard"]} {
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append pc "\nexport_hardware \[get_files ./planahead/xps_files/leon3_zedboard/leon3_zedboard.xmp\] \[get_runs impl_1\] -bitstream"
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}
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set phfile [open "planahead/$TOP\_planAhead_run.tcl" w]
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puts $phfile $pc
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close $phfile
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set phfile [open "planahead/$TOP\_planAhead_end.tcl" w]
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puts $phfile "exit\n"
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close $phfile
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return
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}
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