mirror of
https://github.com/lcbcFoo/ReonV.git
synced 2025-04-18 18:44:43 -04:00
141 lines
1.7 KiB
Text
141 lines
1.7 KiB
Text
XTECHLIBS
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GRLIB
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LIBADD
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FILEADD
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EXTRALIBS
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DIRADD
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TECHLIBS
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XLIBSKIP
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GRLIB_LEON3_VERSION
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XDIRSKIP
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GRLIB_CONFIG
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XFILESKIP
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VHDLANOPT
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VLOGANOPT
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SVLOGANOPT
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VCOM
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VHDLOPT
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VLOG
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SVLOG
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SYNPVHDL
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DCVHDL
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RTLCVHDL
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XSTVHDL
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VIVADOVHDL
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ACOM
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NCVHDL
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XDCLIBSKIP
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XDCDIRSKIP
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DCSKIP
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XSYNPLIBSKIP
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XSYNPDIRSKIP
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SYNPSKIP
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XSTLIBSKIP
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XSTDIRSKIP
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XSTSKIP
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VIVADOLIBSKIP
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VIVADODIRSKIP
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VIVADOSKIP
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GHDLI
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GHDLIOPT
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NCVLOG
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SNPS_HOME
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TOP
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SYNPVLOG
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LIBEROLIBSKIP
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LIBERODIRSKIP
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LIBEROSKIP
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FMVHDL
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FMVHDLOPT
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FMVLOG
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RTLCVLOG
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XSTVLOG
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SF2SIMLIB_RIVIERA
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PLANAHEAD_SIMSET
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PRECDIRSKIP
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PRECLIBSKIP
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PRECSKIP
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ALOG
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QUARTUSLIBSKIP
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QDIRSKIP
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QUARTUSSKIP
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PART
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SPEED
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PACKAGE
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ISPPACKAGE
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LIBERO_PACKAGE
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DESIGNER_PACKAGE
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MGCPACKAGE
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ISPLIB
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TECHNOLOGY
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DESIGNER_TECHNOLOGY
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MGCTECHNOLOGY
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LIBERO_DIE
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DESIGNER_VOLTAGE
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DESIGNER_TEMPR
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DESIGNER_VOLTRANGE
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DESIGNER_PINS
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DESIGNER_PARTR
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MANUFACTURER
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MGCPART
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ISETECH
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QSF
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VHDLOPTSYNFILES
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VHDLSYNFILES
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UCF
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GRLIB_SIMULATOR
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SIMTOP
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VHDLSIMFILES
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PRECOPT
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SYNFREQ
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ISE11TECH
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NETLISTTECH
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XSTOPT
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EFFORT
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GRLIB_XIL_PN_Pack_Reg_Latches_into_IOBs
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QSF_APPEND
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GRLIB_XIL_PN_Simulator
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ISEMAPOPT
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SYNPVLOGDEFS
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VERILOGSYNFILES
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VERILOGOPTSYNFILES
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VERILOGSIMFILES
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SDCFILE
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SDC
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PDC
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LIBERO_EXTRA_SDC
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LIBEROPRECOMPLIBDIR
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DCVLOG
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VIVADOVLOG
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DESIGNER_LAYOUT_OPT
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DESIGNER_RADEXP
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SDC_EXTRA
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PDC_EXTRA
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DESIGNER_PART
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DESIGNER_PACKAGE
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DESIGN
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DEVICE
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GRLIB_XIL_PlanAhead_Simulator
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PROTOBOARD
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CONFIG_MIG_DDR2
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UCF_PLANAHEAD
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PLANAHEAD_BITGEN
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GRLIB_XIL_PlanAhead_sim_verilog_define
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PLANAHEAD_SYNTH_STRATEGY
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PLANAHEAD_IMPL_STRATEGY
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GRLIB_XIL_Vivado_sim_verilog_define
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XDC
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TCL
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VIVADO_UCF
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GRLIB_XIL_Vivado_Simulator
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CONFIG_MIG_7SERIES
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VIVADO_MIG_AXI
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AXI_64
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AXI_128
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CONFIG_GRETH_ENABLE
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VIVADO_SYNTH_FLOW
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VIVADO_SYNTH_STRATEGY
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VIVADO_IMPL_STRATEGY
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VIVADO_SIMSET
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GRLIB_VIVADO_SOURCE_MGMT_MODE
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BOARD
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