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refractoring/cleaning
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parent
62a55c4cf4
commit
2cb0e90077
3 changed files with 12 additions and 13 deletions
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@ -11,7 +11,7 @@ object STATIC extends BranchPrediction
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object DYNAMIC extends BranchPrediction
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class BranchPlugin(earlyBranch : Boolean,
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catchUnalignedException : Boolean,
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catchAddressMisaligned : Boolean,
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prediction : BranchPrediction,
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historyRamSizeLog2 : Int = 10,
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historyWidth : Int = 2) extends Plugin[VexRiscv]{
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@ -71,7 +71,7 @@ class BranchPlugin(earlyBranch : Boolean,
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if (prediction != NONE)
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predictionJumpInterface = pcManagerService.createJumpInterface(pipeline.decode)
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if (catchUnalignedException) {
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if (catchAddressMisaligned) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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branchExceptionPort = exceptionService.newExceptionPort(if (earlyBranch) pipeline.execute else pipeline.memory)
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if (prediction != NONE) {
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@ -130,7 +130,7 @@ class BranchPlugin(earlyBranch : Boolean,
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stages(indexOf(branchStage) - 1).arbitration.flushAll := True
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}
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if(catchUnalignedException) {
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if(catchAddressMisaligned) {
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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branchExceptionPort.code := 0
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branchExceptionPort.badAddr := jumpInterface.payload
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@ -181,7 +181,7 @@ class BranchPlugin(earlyBranch : Boolean,
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fetch.arbitration.flushAll := True
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}
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if(catchUnalignedException) {
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if(catchAddressMisaligned) {
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predictionExceptionPort.valid := input(PREDICTION_HAD_BRANCHED) && arbitration.isValid && predictionJumpInterface.payload(1 downto 0) =/= 0
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predictionExceptionPort.code := 0
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predictionExceptionPort.badAddr := predictionJumpInterface.payload
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@ -237,7 +237,7 @@ class BranchPlugin(earlyBranch : Boolean,
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stages(indexOf(branchStage) - 1).arbitration.flushAll := True
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}
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if(catchUnalignedException) {
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if(catchAddressMisaligned) {
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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branchExceptionPort.code := 0
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branchExceptionPort.badAddr := jumpInterface.payload
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@ -18,7 +18,7 @@ case class DBusSimpleRsp() extends Bundle{
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val data = Bits(32 bit)
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}
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class DBusSimplePlugin(catchUnalignedException : Boolean, catchAccessFault : Boolean) extends Plugin[VexRiscv]{
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class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean) extends Plugin[VexRiscv]{
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var dCmd : Stream[DBusSimpleCmd] = null
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var dRsp : DBusSimpleRsp = null
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@ -45,9 +45,8 @@ class DBusSimplePlugin(catchUnalignedException : Boolean, catchAccessFault : Boo
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SRC1_CTRL -> Src1CtrlEnum.RS,
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SRC_USE_SUB_LESS -> False,
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MEMORY_ENABLE -> True,
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REG1_USE -> True,
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IntAluPlugin.ALU_CTRL -> IntAluPlugin.AluCtrlEnum.ADD_SUB //Used for assess fault bad address in memory stage
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)
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REG1_USE -> True
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) ++ (if(catchAccessFault) List(IntAluPlugin.ALU_CTRL -> IntAluPlugin.AluCtrlEnum.ADD_SUB) else Nil) //Used for access fault bad address in memory stage
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val loadActions = stdActions ++ List(
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SRC2_CTRL -> Src2CtrlEnum.IMI,
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@ -74,7 +73,7 @@ class DBusSimplePlugin(catchUnalignedException : Boolean, catchAccessFault : Boo
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SW -> (storeActions)
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))
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if(catchUnalignedException) {
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if(catchAddressMisaligned) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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executeExceptionPort = exceptionService.newExceptionPort(pipeline.execute)
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}
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@ -109,7 +108,7 @@ class DBusSimplePlugin(catchUnalignedException : Boolean, catchAccessFault : Boo
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insert(MEMORY_ADDRESS_LOW) := dCmd.address(1 downto 0)
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if(catchUnalignedException){
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if(catchAddressMisaligned){
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executeExceptionPort.code := (dCmd.wr ? U(6) | U(4)).resized
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executeExceptionPort.badAddr := dCmd.address
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executeExceptionPort.valid := (arbitration.isValid && input(MEMORY_ENABLE)
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@ -85,7 +85,7 @@ object TopLevel {
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new FullBarrielShifterPlugin,
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// new LightShifterPlugin,
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new DBusSimplePlugin(
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catchUnalignedException = true,
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catchAddressMisaligned = true,
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catchAccessFault = true
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),
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new HazardSimplePlugin(true, true, true, true),
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@ -96,7 +96,7 @@ object TopLevel {
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new MachineCsr(csrConfig),
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new BranchPlugin(
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earlyBranch = false,
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catchUnalignedException = true,
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catchAddressMisaligned = true,
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prediction = DYNAMIC
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)
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)
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