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Add tests for iRsp, dRsp access faults

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This commit is contained in:
Charles Papon 2017-03-28 20:25:58 +02:00
parent 2cb0e90077
commit 32d32845bd
6 changed files with 35 additions and 15 deletions
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2
src/main/scala/SpinalRiscv/Plugin/IBusSimplePlugin.scala
View file

@ -26,7 +26,7 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
if(catchAccessFault) {
val exceptionService = pipeline.service(classOf[ExceptionService])
decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode)
decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1)
}
}

12
src/main/scala/SpinalRiscv/Plugin/MachineCsr.scala
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@ -20,7 +20,7 @@ object CsrAccess {
object NONE extends CsrAccess
}
case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage)
case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage, priority : Int)
case class MachineCsrConfig(
mvendorid : BigInt,
marchid : BigInt,
@ -71,9 +71,9 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
//Mannage ExceptionService calls
val exceptionPortsInfos = ArrayBuffer[ExceptionPortInfo]()
def exceptionCodeWidth = 4
override def newExceptionPort(stage : Stage) = {
override def newExceptionPort(stage : Stage, priority : Int = 0) = {
val interface = Flow(ExceptionCause())
exceptionPortsInfos += ExceptionPortInfo(interface,stage)
exceptionPortsInfos += ExceptionPortInfo(interface,stage,priority)
interface
}
@ -248,7 +248,7 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
val groupedByStage = exceptionPortsInfos.map(_.stage).distinct.map(s => {
assert(s != writeBack)
val stagePortsInfos = exceptionPortsInfos.filter(_.stage == s)
val stagePortsInfos = exceptionPortsInfos.filter(_.stage == s).sortWith(_.priority > _.priority)
val stagePort = stagePortsInfos.length match{
case 1 => stagePortsInfos.head.port
case _ => {
@ -256,11 +256,11 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
val valids = stagePortsInfos.map(_.port.valid)
val codes = stagePortsInfos.map(_.port.payload)
groupedPort.valid := valids.orR
groupedPort.payload := MuxOH(stagePortsInfos.map(_.port.valid), codes)
groupedPort.payload := MuxOH(OHMasking.first(stagePortsInfos.map(_.port.valid).asBits), codes)
groupedPort
}
}
ExceptionPortInfo(stagePort,s)
ExceptionPortInfo(stagePort,s,0)
})
val sortedByStage = groupedByStage.sortWith((a, b) => pipeline.indexOf(a.stage) < pipeline.indexOf(b.stage))

2
src/main/scala/SpinalRiscv/Services.scala
View file

@ -19,5 +19,5 @@ case class ExceptionCause() extends Bundle{
}
trait ExceptionService{
def newExceptionPort(stage : Stage) : Flow[ExceptionCause]
def newExceptionPort(stage : Stage, priority : Int = 0) : Flow[ExceptionCause]
}

17
src/test/cpp/testA/main.cpp
View file

@ -177,6 +177,7 @@ public:
Workspace* bootAt(uint32_t pc) { bootPc = pc;}
virtual uint32_t iRspOverride(uint32_t value) { return value; }
virtual bool isAccessError(uint32_t addr) { return addr == 0xF00FFF60u; }
virtual void postReset() {}
virtual void checks(){}
virtual void pass(){ throw success();}
@ -233,6 +234,7 @@ public:
// run simulation for 100 clock periods
uint32_t iRsp_inst_next = top->iRsp_inst;
uint32_t dRsp_inst_next = VL_RANDOM_I(32);
bool iRsp_error_next = false, dRsp_error_next = false;
bool iRsp_ready_pending = false, dRsp_ready_pending = false;
for (i = 16; i < timeout*2; i+=2) {
mTime = i/2;
@ -262,16 +264,15 @@ public:
| (mem[top->iCmd_payload_pc + 1] << 8)
| (mem[top->iCmd_payload_pc + 2] << 16)
| (mem[top->iCmd_payload_pc + 3] << 24));
iRsp_error_next = isAccessError(top->iCmd_payload_pc);
}
if (top->dCmd_valid && top->dCmd_ready && ! dRsp_ready_pending) {
// assertEq(top->iCmd_payload_pc & 3,0);
dRsp_ready_pending = true;
dRsp_inst_next = VL_RANDOM_I(32);
//printf("%d\n",top->iCmd_payload_pc);
uint32_t addr = top->dCmd_payload_address;
dRsp_error_next = isAccessError(addr);
if(top->dCmd_payload_wr){
memTraces <<
#ifdef TRACE_WITH_TIME
@ -344,11 +345,13 @@ public:
top->iRsp_inst = iRsp_inst_next;
iRsp_ready_pending = false;
top->iRsp_ready = 1;
top->iRsp_error = iRsp_error_next;
}
if(dRsp_ready_pending && (!dStall || VL_RANDOM_I(8) < 100)){
top->dRsp_data = dRsp_inst_next;
dRsp_ready_pending = false;
top->dRsp_ready = 1;
top->dRsp_error = dRsp_error_next;
} else{
top->dRsp_data = VL_RANDOM_I(32);
}
@ -618,7 +621,7 @@ int main(int argc, char **argv, char **env) {
#ifdef CSR
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
8,6,9,6,10,4,11,4, 12,13,0, 14,2,15 };
8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,5,17,1 };
redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).run(4e3);)
#endif
#endif
@ -628,9 +631,9 @@ int main(int argc, char **argv, char **env) {
#ifdef DHRYSTONE
// Dhrystone("dhrystoneO3",false,false).run(0.05e6);
Dhrystone("dhrystoneO3",true,true).run(1.1e6);
Dhrystone("dhrystoneO3M",true,true).run(0.8e6);
Dhrystone("dhrystoneO3",false,false).run(1.1e6);
Dhrystone("dhrystoneO3M",false,false).run(0.8e6);
Dhrystone("dhrystoneO3M",true,true).run(1.5e6);
Dhrystone("dhrystoneO3",false,false).run(1.5e6);
Dhrystone("dhrystoneO3M",false,false).run(1.2e6);
// Dhrystone("dhrystoneO3ML",false,false).run(8e6);
// Dhrystone("dhrystoneO3MLL",false,false).run(80e6);
#endif

15
src/test/resources/asm/machineCsr.asm
View file

@ -266,6 +266,21 @@ unalignedPcA:
li x28, 15
1ac: 00f00e13 li t3,15
li x1, 0xF00FFF60
1b0: f01000b7 lui ra,0xf0100
1b4: f6008093 addi ra,ra,-160 # f00fff60 <_bss_end+0xb00f38d8>
lw x2, 0(x1)
1b8: 0000a103 lw sp,0(ra)
li x28, 16
1bc: 01000e13 li t3,16
sw x2, 0(x1)
1c0: 0020a023 sw sp,0(ra)
li x28, 17
1c4: 01100e13 li t3,17
jr x1
1c8: 00008067 ret
Disassembly of section .text:
40000000 <fstat>:

2
src/test/resources/hex/machineCsr.hex
View file

@ -25,6 +25,8 @@
:10018000130EA00003A20100130EB00003920100A1
:10019000130EC000130ED000832000006F0020005B
:1001A00083200000130EE00073002020130EF000E7
:1001B000B70010F0938000F603A10000130E0001B9
:0C01C00023A02000130E10016780000037
:020000044000BA
:1000000013050000678000001305000067800000F2
:1000100097020000678082FF1305000067800000E0