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https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
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Using P opcodes (and double-width/read-rs3-from-rd behavior) to try some custom Chacha-oriented instructions
This commit is contained in:
Romain Dolbeau
parent
bb182d099d
commit
29738d20b8
6 changed files with 145 additions and 8 deletions
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@ -41,3 +41,29 @@ kernelrandombytes.o: random.cpp
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cpucycles.o: riscv.c
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$(R5IMA_GCC) $< -march=rv32ima -mabi=ilp32 -I. -O1 -c -o $@
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chacha_XAR.S: chacha.c
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$(R5B_GCC) $(R5B_OPT) -DENABLE_XAR $< -S -o $@
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chacha_XAR.o: chacha_XAR.S
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$(R5B_GCC) $(R5B_OPT) -DENABLE_XAR $< -c -o $@
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chacha20_XAR: $(OBJs) chacha_XAR.o try.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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chacha20_XAR_small: $(OBJs) chacha_XAR.o try_small.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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chacha_CHACHA.S: chacha.c
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$(R5B_GCC) $(R5B_OPT) -O3 -DENABLE_CHACHA $< -S -o $@
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chacha_CHACHA.o: chacha_CHACHA.S
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$(R5B_GCC) $(R5B_OPT) -O3 -DENABLE_CHACHA $< -c -o $@
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chacha20_CHACHA: $(OBJs) chacha_CHACHA.o try.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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chacha20_CHACHA_small: $(OBJs) chacha_CHACHA.o try_small.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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@ -21,12 +21,61 @@ Public domain.
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#define PLUS(v,w) (U32V((v) + (w)))
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#define PLUSONE(v) (PLUS((v),1))
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#if !defined(ENABLE_XAR) && !defined(ENABLE_CHACHA)
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#define QUARTERROUND(a,b,c,d) \
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x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]),16); \
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x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]),12); \
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x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]), 8); \
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x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]), 7);
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#define QUARTERROUND1(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND2(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND3(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND4(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND5(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND6(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND7(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND8(a,b,c,d) QUARTERROUND(a,b,c,d)
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#elif !defined(ENABLE_CHACHA)
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#define QUARTERROUND(a,b,c,d) \
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x[a] = PLUS(x[a],x[b]); x[d] = __rv__xar(x[a],16,x[d]); \
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x[c] = PLUS(x[c],x[d]); x[b] = __rv__xar(x[c],12,x[b]); \
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x[a] = PLUS(x[a],x[b]); x[d] = __rv__xar(x[a], 8,x[d]); \
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x[c] = PLUS(x[c],x[d]); x[b] = __rv__xar(x[c], 7,x[b]);
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#define QUARTERROUND1(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND2(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND3(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND4(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND5(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND6(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND7(a,b,c,d) QUARTERROUND(a,b,c,d)
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#define QUARTERROUND8(a,b,c,d) QUARTERROUND(a,b,c,d)
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#else
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#define QUARTERROUNDx(a,b,c,d,r0,r1,r2,r3) \
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{ \
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register uint32_t A asm(""#r0) = x[a]; \
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register uint32_t D asm(""#r1) = x[d]; \
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register uint32_t C asm(""#r2) = x[c]; \
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register uint32_t B asm(""#r3) = x[b]; \
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asm("CHACHA16 reg_%0, reg_%1, reg_%3\n" \
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"CHACHA12 reg_%2, reg_%3, reg_%1\n" \
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"CHACHA8 reg_%0, reg_%1, reg_%3\n" \
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"CHACHA7 reg_%2, reg_%3, reg_%1\n" \
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: "+&r" (A), "+&r" (B), "+&r" (C), "+&r" (D)); \
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x[a] = A; x[b] = B; x[c] = C; x[d] = D; \
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}
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#define QUARTERROUND1(a,b,c,d) QUARTERROUNDx(a,b,c,d,t3,t4,t5,t6)
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#define QUARTERROUND2(a,b,c,d) QUARTERROUNDx(a,b,c,d,s8,s9,s10,s11)
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#define QUARTERROUND3(a,b,c,d) QUARTERROUNDx(a,b,c,d,s4,s5,s6,s7)
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#define QUARTERROUND4(a,b,c,d) QUARTERROUNDx(a,b,c,d,a6,a7,s2,s3)
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#define QUARTERROUND5(a,b,c,d) QUARTERROUNDx(a,b,c,d,t3,t4,s6,s7)
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#define QUARTERROUND6(a,b,c,d) QUARTERROUNDx(a,b,c,d,s8,s9,s2,s3)
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#define QUARTERROUND7(a,b,c,d) QUARTERROUNDx(a,b,c,d,s4,s5,t5,t6)
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#define QUARTERROUND8(a,b,c,d) QUARTERROUNDx(a,b,c,d,a6,a7,s10,s11)
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#endif
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static void salsa20_wordtobyte(u8 output[64],const u32 input[16])
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{
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u32 x[16];
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@ -34,14 +83,14 @@ static void salsa20_wordtobyte(u8 output[64],const u32 input[16])
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for (i = 0;i < 16;++i) x[i] = input[i];
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for (i = ROUNDS;i > 0;i -= 2) {
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QUARTERROUND( 0, 4, 8,12)
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QUARTERROUND( 1, 5, 9,13)
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QUARTERROUND( 2, 6,10,14)
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QUARTERROUND( 3, 7,11,15)
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QUARTERROUND( 0, 5,10,15)
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QUARTERROUND( 1, 6,11,12)
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QUARTERROUND( 2, 7, 8,13)
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QUARTERROUND( 3, 4, 9,14)
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QUARTERROUND1( 0, 4, 8,12)
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QUARTERROUND2( 1, 5, 9,13)
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QUARTERROUND3( 2, 6,10,14)
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QUARTERROUND4( 3, 7,11,15)
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QUARTERROUND5( 0, 5,10,15)
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QUARTERROUND6( 1, 6,11,12)
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QUARTERROUND7( 2, 7, 8,13)
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QUARTERROUND8( 3, 4, 9,14)
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}
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for (i = 0;i < 16;++i) x[i] = PLUS(x[i],input[i]);
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for (i = 0;i < 16;++i) U32TO8_LITTLE(output + 4 * i,x[i]);
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24
data_Chacha64.txt
Normal file
24
data_Chacha64.txt
Normal file
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@ -0,0 +1,24 @@
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//for vX.Y of P
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// low-order bit of Rd (7) is 0 to ensure even-numbered Rd
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I CHACHA CHACHA 101--00----------000----01110111 chacha Zchacha
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S CHACHA "fun_chacha(input(SRC1), input(SRC2), input(SRC3), input(INSTRUCTION)(28 downto 27))"
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P """
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def fun_chacha(rs1: Bits, rs2: Bits, rs3: Bits, num: Bits) : Bits = {
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val rotv = (num).mux(
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B"2'b00" -> U(16),
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B"2'b01" -> U(12),
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B"2'b10" -> U( 8),
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B"2'b11" -> U( 7)
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)
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val a = rs3
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val b = rs1
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val d = rs2
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val sum = (a.asUInt + b.asUInt).asBits.resize(32)
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val xor = sum ^ d
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val rot = xor.rotateLeft(rotv)
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rot ## sum // return value
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}
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"""
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11
data_xar.txt
Normal file
11
data_xar.txt
Normal file
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@ -0,0 +1,11 @@
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I XAR XAR 1100100----------000-----1110111 xar Zbxar
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S XAR "fun_xar(input(SRC1), input(SRC2), input(SRC3))"
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P """
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def fun_xar(rs1: Bits, rs2: Bits, rs3: Bits) : Bits = {
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val in = rs1 ^ rs3
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val r = in.rotateLeft(rs2(4 downto 0).asUInt)
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r // return value
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}
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"""
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@ -73,6 +73,21 @@ typedef uint32_t uint_xlen_t;
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return ((uint64_t)r0 | (((uint64_t)r1)<<32)); \
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}
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// ternary wide (64-bits output in R2n/R2n+1)
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#define FUN3Wx(NAME, ASNAME, r0, r1) \
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static inline uint64_t NAME(uint_xlen_t rs1, uint_xlen_t rs2, uint_xlen_t rs3) { \
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register uint32_t r0 asm (""#r0), r1 asm (""#r1); \
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r0 = rs3; \
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asm (#ASNAME " reg_%0, reg_%2, reg_%3\n" \
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: "+r" (r0), "=r" (r1) \
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: "r" (rs1), "r" (rs2)); \
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return ((uint64_t)r0 | (((uint64_t)r1)<<32)); \
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}
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#define FUN3Wt5(NAME, ASNAME) FUN3Wx(NAME, ASNAME, t5, t6)
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#define FUN3Wt3(NAME, ASNAME) FUN3Wx(NAME, ASNAME, t3, t4)
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#define FUN3Ws10(NAME, ASNAME) FUN3Wx(NAME, ASNAME, s10, s11)
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#define FUN3Ws8(NAME, ASNAME) FUN3Wx(NAME, ASNAME, s8, s9)
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// macro to build assembly macros to generate the proper
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// opcodes as .word macro
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// the translation from name to number is done my the
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@ -19,4 +19,16 @@ FUN2(_sh1add,_SH1ADD)
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FUN2(_sh2add,_SH2ADD)
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FUN2(_sh3add,_SH3ADD)
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#ifdef ENABLE_XAR
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ASM3RMACRO(XAR, 0xc8000077)
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FUN3R(__rv__xar, XAR)
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#endif
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#ifdef ENABLE_CHACHA
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ASM3RMACRO(CHACHA16,0xa0000077)
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ASM3RMACRO(CHACHA12,0xa8000077)
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ASM3RMACRO(CHACHA8, 0xb0000077)
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ASM3RMACRO(CHACHA7, 0xb8000077)
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#endif
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#endif // __NEW_INSTRUCTION_SUPPORT_B_H__
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