mirror of
https://github.com/rdolbeau/VexRiscvBPluginGenerator.git
synced 2025-04-18 18:44:42 -04:00
69 lines
1.6 KiB
Makefile
69 lines
1.6 KiB
Makefile
SRCs=api.c try-anything.c
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OBJs=$(SRCs:.c=.o)
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SCLIBS=cpucycles.o kernelrandombytes.o
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include ../r5.mk
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R5IMA_OPT+=-I..
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R5B_OPT+=-I.. -DRV32B -DRV32K
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all: chacha20 chacha20_small
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clean:
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rm -f $(OBJs) *.S try.o try_small.o chacha.o chacha20 chacha20_small chacha20_small_var chacha.s chacha_var.s
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%.o: %.c
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$(R5IMA_GCC) $(R5IMA_OPT) $< -c -o $@
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try.o: try.c
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$(R5IMA_GCC) $(R5IMA_OPT) $< -c -o $@
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try_small.o: try.c
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$(R5IMA_GCC) $(R5IMA_OPT) $< -c -o $@ -DSMALL
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chacha.S: chacha.c
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$(R5B_GCC) $(R5B_OPT) $< -S -o $@
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chacha.o: chacha.S
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$(R5B_GCC) $(R5B_OPT) $< -c -o $@
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chacha20: $(OBJs) chacha.o try.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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chacha20_small: $(OBJs) chacha.o try_small.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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strip:
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$(STRIP) chacha20 chacha20_small
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kernelrandombytes.o: random.cpp
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$(R5IMA_GXX) $(R5IMA_OPT) $< -c -o $@
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cpucycles.o: riscv.c
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$(R5IMA_GCC) $< -march=rv32ima -mabi=ilp32 -I. -O1 -c -o $@
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chacha_XAR.S: chacha.c
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$(R5B_GCC) $(R5B_OPT) -DENABLE_XAR $< -S -o $@
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chacha_XAR.o: chacha_XAR.S
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$(R5B_GCC) $(R5B_OPT) -DENABLE_XAR $< -c -o $@
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chacha20_XAR: $(OBJs) chacha_XAR.o try.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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chacha20_XAR_small: $(OBJs) chacha_XAR.o try_small.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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chacha_CHACHA.S: chacha.c
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$(R5B_GCC) $(R5B_OPT) -O3 -DENABLE_CHACHA $< -S -o $@
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chacha_CHACHA.o: chacha_CHACHA.S
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$(R5B_GCC) $(R5B_OPT) -O3 -DENABLE_CHACHA $< -c -o $@
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chacha20_CHACHA: $(OBJs) chacha_CHACHA.o try.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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chacha20_CHACHA_small: $(OBJs) chacha_CHACHA.o try_small.o $(SCLIBS)
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$(R5IMA_GXX) $(R5IMA_OPT) $^ -o $@
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