further code cleanup

core/alu_unit.sv

@@ -27,8 +27,8 @@ module alu_unit(
         input logic clk,
         input logic rst,
         unit_issue_interface.unit issue,
-        unit_writeback_interface.unit wb,
-        input alu_inputs_t alu_inputs
+        input alu_inputs_t alu_inputs,
+        output unit_writeback_t wb
         );
 
     logic[XLEN:0] add_sub_result;

core/div_unit.sv

@@ -30,7 +30,7 @@ module div_unit
 
         input div_inputs_t div_inputs,
         unit_issue_interface.unit issue,
-        unit_writeback_interface.unit wb
+        output unit_writeback_t wb
     );
 
     logic computation_complete;

core/interfaces.sv

@@ -73,24 +73,6 @@ interface ras_interface;
     modport fetch (input addr, valid);
 endinterface
 
-interface unit_writeback_interface;
-    //unit output
-    instruction_id_t id;
-    logic done_next_cycle;
-    logic [XLEN-1:0] rd;
-    logic [XLEN-1:0] rs1_data;
-    logic [XLEN-1:0] rs2_data;
-    //writeback output
-    logic accepted;
-    instruction_id_t writeback_instruction_id;
-    instruction_id_t writeback_rs1_id;
-    instruction_id_t writeback_rs2_id;
-    modport writeback (input id, done_next_cycle, rd, rs1_data, rs2_data, output accepted, writeback_instruction_id, writeback_rs1_id, writeback_rs2_id);
-    modport unit (output id, done_next_cycle, rd, rs1_data, rs2_data, input accepted, writeback_instruction_id, writeback_rs1_id, writeback_rs2_id);
-endinterface
-
-//********************************
-
 interface csr_exception_interface;
     logic valid;
     exception_code_t code;
@@ -148,16 +130,14 @@ interface register_file_writeback_interface;
 
     instruction_id_t rs1_id;
     instruction_id_t rs2_id;
-    unit_id_t rs1_unit_id;
-    unit_id_t rs2_unit_id;
 
     logic[XLEN-1:0] rs1_data;
     logic[XLEN-1:0] rs2_data;
     logic rs1_valid;
     logic rs2_valid;
     
-    modport writeback (output rd_addr, commit, rd_nzero, rd_data, id, rs1_data, rs2_data, rs1_valid, rs2_valid,  input rs1_id, rs2_id, rs1_unit_id, rs2_unit_id);
-    modport unit (input rd_addr, commit, rd_nzero, rd_data, id, rs1_data, rs2_data, rs1_valid, rs2_valid, output rs1_id, rs2_id, rs1_unit_id, rs2_unit_id);
+    modport writeback (output rd_addr, commit, rd_nzero, rd_data, id, rs1_data, rs2_data, rs1_valid, rs2_valid,  input rs1_id, rs2_id);
+    modport unit (input rd_addr, commit, rd_nzero, rd_data, id, rs1_data, rs2_data, rs1_valid, rs2_valid, output rs1_id, rs2_id);
 
 endinterface
 

core/load_store_unit.sv

@@ -53,7 +53,7 @@ module load_store_unit (
         output exception_packet_t ls_exception,
         output logic ls_exception_valid,
 
-        unit_writeback_interface.unit wb
+        output unit_writeback_t wb
         );
 
     localparam NUM_SUB_UNITS = USE_D_SCRATCH_MEM+USE_BUS+USE_DCACHE;

core/mul_unit.sv

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2017 Eric Matthews,  Lesley Shannon
+ * Copyright © 2017-2019 Eric Matthews,  Lesley Shannon
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -29,7 +29,7 @@ module mul_unit(
 
         input mul_inputs_t mul_inputs,
         unit_issue_interface.unit issue,
-        unit_writeback_interface.unit wb
+        output unit_writeback_t wb
         );
 
     logic signed [65:0] result;

core/register_file.sv

@@ -48,9 +48,6 @@ module register_file(
 
     logic valid_write;
     logic in_use_match;
-
-    instruction_id_t rs1_id;
-    instruction_id_t rs2_id;
     //////////////////////////////////////////
     //Assign zero to r0 and initialize all registers to zero
     initial begin

core/taiga.sv

@@ -67,7 +67,7 @@ module taiga (
     logic ls_exception_valid;
 
     tracking_interface ti();
-    unit_writeback_interface unit_wb [NUM_WB_UNITS-1:0]();
+    unit_writeback_t unit_wb [NUM_WB_UNITS-1:0];
     register_file_writeback_interface rf_wb();
 
     mmu_interface immu();

core/taiga_types.sv

@@ -295,6 +295,11 @@ package taiga_types;
         alu_rs2_op_t alu_rs2_sel;
     } fetch_buffer_packet_t;
 
+    typedef struct packed{
+        instruction_id_t id;
+        logic done_next_cycle;
+        logic [XLEN-1:0] rd;
+    } unit_writeback_t;
 
     typedef struct packed{
         logic [XLEN:0] in1;//contains sign padding bit for slt operation

core/write_back.sv

@@ -29,7 +29,7 @@ module write_back(
 
         input logic instruction_issued_with_rd,
 
-        unit_writeback_interface.writeback unit_wb[NUM_WB_UNITS-1:0],
+        input unit_writeback_t unit_wb[NUM_WB_UNITS-1:0],
         register_file_writeback_interface.writeback rf_wb,
         tracking_interface.wb ti,
         output logic instruction_complete,
@@ -41,7 +41,7 @@ module write_back(
         );
     //////////////////////////////////////
 
-    //Inflight packets
+    //Inflight packetscd
     logic[$bits(inflight_instruction_packet)-1:0] packet_table [MAX_INFLIGHT_COUNT-1:0];
 
     //aliases for write-back-interface signals