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code cleanup

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This commit is contained in:
Eric Matthews 2019-09-01 20:44:13 -07:00
parent 89ae201b30
commit a34714db52
4 changed files with 10 additions and 51 deletions
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2
core/decode.sv
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@ -148,8 +148,6 @@ module decode(
assign ti.inflight_packet.rd_addr = future_rd_addr;
assign ti.inflight_packet.rd_addr_nzero = ~rd_zero;
assign ti.inflight_packet.is_store = (opcode_trim == STORE_T) || (amo_op && store_conditional);
assign ti.inflight_packet.id = ti.issue_id;
assign ti.inflight_packet.unit_id = unit_id;
assign ti.issued = instruction_issued & (uses_rd | new_request[LS_UNIT_WB_ID]);
////////////////////////////////////////////////////

30
core/register_file.sv
View file

@ -37,18 +37,8 @@ module register_file(
output logic tr_rs1_and_rs2_forwarding_needed
);
typedef struct packed{
instruction_id_t id;
unit_id_t unit_id;
} register_id_store_t;
(* ramstyle = "MLAB, no_rw_check" *) logic [XLEN-1:0] register [31:0];
(* ramstyle = "MLAB, no_rw_check" *) logic[$bits(register_id_store_t)-1:0] in_use_by [31:0];
register_id_store_t new_id_store;
register_id_store_t rs1_usage;
register_id_store_t rs2_usage;
register_id_store_t wb_usage;
(* ramstyle = "MLAB, no_rw_check" *) instruction_id_t in_use_by [31:0];
logic rs1_inuse;
logic rs2_inuse;
@ -86,24 +76,14 @@ module register_file(
.rs2_inuse(rs2_inuse)
);
assign new_id_store.id = rf_decode.id;
assign new_id_store.unit_id = rf_decode.unit_id;
always_ff @ (posedge clk) begin
if (rf_decode.instruction_issued)
in_use_by[rf_decode.future_rd_addr] <= new_id_store;
in_use_by[rf_decode.future_rd_addr] <= rf_decode.id;
end
assign rs1_usage = in_use_by[rf_decode.rs1_addr];
assign rs2_usage = in_use_by[rf_decode.rs2_addr];
assign wb_usage = in_use_by[rf_wb.rd_addr];
assign in_use_match = (wb_usage.id == rf_wb.id);
assign rf_wb.rs1_id = rs1_usage.id;
assign rf_wb.rs2_id = rs2_usage.id;
assign rf_wb.rs1_unit_id = rs1_usage.unit_id;
assign rf_wb.rs2_unit_id = rs2_usage.unit_id;
assign in_use_match = (rf_wb.id == in_use_by[rf_wb.rd_addr]);
assign rf_wb.rs1_id = in_use_by[rf_decode.rs1_addr];
assign rf_wb.rs2_id = in_use_by[rf_decode.rs2_addr];
assign valid_write = rf_wb.rd_nzero & rf_wb.commit;

2
core/taiga_types.sv
View file

@ -270,8 +270,6 @@ package taiga_types;
} exception_packet_t;
typedef struct packed{
instruction_id_t id;
unit_id_t unit_id;
logic [4:0] rd_addr;
logic rd_addr_nzero;
logic is_store;

27
core/write_back.sv
View file

@ -48,27 +48,19 @@ module write_back(
instruction_id_t unit_instruction_id [NUM_WB_UNITS-1:0];
logic [NUM_WB_UNITS-1:0] unit_done_next_cycle;
logic [XLEN-1:0] unit_rd [NUM_WB_UNITS-1:0];
logic [XLEN-1:0] unit_rs1 [NUM_WB_UNITS-1:0];
logic [XLEN-1:0] unit_rs2 [NUM_WB_UNITS-1:0];
/////
logic [XLEN-1:0] rds_by_id [MAX_INFLIGHT_COUNT-1:0];
logic [XLEN-1:0] rds_by_id_next [MAX_INFLIGHT_COUNT-1:0];
logic [NUM_WB_UNITS-1:0][MAX_INFLIGHT_COUNT-1:0] write_reg;
logic [$clog2(NUM_WB_UNITS)-1:0] id_unit_select [MAX_INFLIGHT_COUNT-1:0];
instruction_id_t issue_id, retired_id, retired_id_r;
inflight_instruction_packet retired_instruction_packet;
inflight_instruction_packet rs1_packet;
inflight_instruction_packet rs2_packet;
logic [MAX_INFLIGHT_COUNT-1:0] id_done;
logic [MAX_INFLIGHT_COUNT-1:0] id_done_new;
logic [MAX_INFLIGHT_COUNT-1:0] id_done_r;
logic [MAX_INFLIGHT_COUNT-1:0] id_done_ordered;
logic [MAX_INFLIGHT_COUNT-1:0] id_done_ordered_post_store;
logic retired, retired_r;
////////////////////////////////////////////////////
//Implementation
@ -90,7 +82,7 @@ module write_back(
for (int j=0; j< NUM_WB_UNITS; j++) begin
if (unit_done_next_cycle[j] && (unit_instruction_id[j] == i[$clog2(MAX_INFLIGHT_COUNT)-1:0])) begin
id_unit_select[i] = j[$clog2(NUM_WB_UNITS)-1:0];
id_done_new[i] |= 1;//unit_done_next_cycle[j] && (unit_instruction_id[j] == i[$clog2(MAX_INFLIGHT_COUNT)-1:0]);
id_done_new[i] |= 1;
end
end
end
@ -115,7 +107,7 @@ module write_back(
assign ti.issue_id = issue_id;
//Inflight Instruction ID table
//Stores unit id (in one-hot encoding), rd_addr and whether rd_addr is zero
//Stores rd_addr and whether rd_addr is zero
initial begin
foreach (packet_table[i]) begin
packet_table[i] = '0;
@ -140,16 +132,7 @@ module write_back(
id_retired_last_cycle_r <= id_retired_last_cycle;
end
//Or together all unit done signals for the same ID.
// always_comb begin
// id_done_new = 0;
// for (int i=0; i < MAX_INFLIGHT_COUNT; i++) begin
// for (int j=0; j< NUM_WB_UNITS; j++) begin
// id_done_new[i] |= unit_done_next_cycle[j] && (unit_instruction_id[j] == i[$clog2(MAX_INFLIGHT_COUNT)-1:0]);
// end
// end
// end
assign id_done = (id_done_r & ~id_retired_last_cycle_r) | id_done_new; //Still pending instructions
assign id_done = (id_done_r & ~id_retired_last_cycle_r) | id_done_new;
always_ff @ (posedge clk) begin
if (rst)
@ -178,7 +161,7 @@ module write_back(
assign rf_wb.id = retired_id_r;
assign rf_wb.commit = retired_r & ~retired_instruction_packet.is_store;
assign rf_wb.rd_nzero = retired_instruction_packet.rd_addr_nzero;
assign rf_wb.rd_data = rds_by_id[retired_id_r];//unit_rd[retired_instruction_packet.unit_id];
assign rf_wb.rd_data = rds_by_id[retired_id_r];
assign rf_wb.rs1_valid = id_done_r[rf_wb.rs1_id];
assign rf_wb.rs2_valid = id_done_r[rf_wb.rs2_id];
@ -200,7 +183,7 @@ module write_back(
tr_wb_mux_contention = 0;
for (int i=0; i<MAX_INFLIGHT_COUNT-1; i++) begin
for (int j=i+1; j<MAX_INFLIGHT_COUNT; j++) begin
tr_wb_mux_contention |= (id_done[i] & id_done[j]);
tr_wb_mux_contention |= (id_done_r[i] & id_done_r[j]);
end
end
end