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Consolidate BRAM implementations

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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews 2023-04-17 13:15:24 -04:00
parent 24baf185e7
commit 17c45f0050
11 changed files with 64 additions and 118 deletions
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2
core/common_components/byte_en_BRAM.sv → core/common_components/byte_en_bram.sv
View file

@ -22,7 +22,7 @@
module byte_en_BRAM
module byte_en_bram
import cva5_config::*;
import cva5_types::*;

47
core/fetch_stage/tag_bank.sv → core/common_components/dual_port_bram.sv Executable file → Normal file
View file

@ -1,5 +1,5 @@
/*
* Copyright © 2017-2020 Eric Matthews, Lesley Shannon
* Copyright © 2023 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -20,46 +20,51 @@
* Eric Matthews <ematthew@sfu.ca>
*/
module tag_bank
#(
module dual_port_bram
import cva5_config::*;
import cva5_types::*;
import riscv_types::*;
#(
parameter WIDTH = 32,
parameter LINES = 512
parameter LINES = 4096
)
(
input logic clk,
input logic rst,
input logic[$clog2(LINES)-1:0] addr_a,
input logic[$clog2(LINES)-1:0] addr_b,
input logic en_a,
input logic en_b,
input logic wen_a,
input logic[$clog2(LINES)-1:0] addr_a,
input logic[WIDTH-1:0] data_in_a,
output logic[WIDTH-1:0] data_out_a,
input logic en_b,
input logic wen_b,
input logic [WIDTH-1:0] data_in_a,
input logic [WIDTH-1:0] data_in_b,
output logic [WIDTH-1:0] data_out_a,
output logic [WIDTH-1:0] data_out_b
input logic[$clog2(LINES)-1:0] addr_b,
input logic[WIDTH-1:0] data_in_b,
output logic[WIDTH-1:0] data_out_b
);
(* ram_style = "block", ramstyle = "no_rw_check" *) logic [WIDTH-1:0] tag_entry [LINES];
initial tag_entry = '{default: 0};
(* ram_style = "block", ramstyle = "no_rw_check" *) logic [WIDTH-1:0] ram [LINES];
initial ram = '{default: 0};
always_ff @ (posedge clk) begin
if (en_a) begin
if (wen_a)
tag_entry[addr_a] <= data_in_a;
else
data_out_a <= tag_entry[addr_a];
ram[addr_a] <= data_in_a;
data_out_a <= ram[addr_a];
end
end
always_ff @ (posedge clk) begin
if (en_b) begin
if (wen_b)
tag_entry[addr_b] <= data_in_b;
else
data_out_b <= tag_entry[addr_b];
ram[addr_b] <= data_in_b;
data_out_b <= ram[addr_b];
end
end
endmodule
endmodule

2
core/execution_units/load_store_unit/dcache.sv
View file

@ -253,7 +253,7 @@ module dcache
assign data_read_addr = load_state[LOAD_FILL] ? {addr_utils.getTagLineAddr(stage2_load.addr), word_count} : addr_utils.getDataLineAddr(ls_load.addr);
generate for (genvar i=0; i < CONFIG.DCACHE.WAYS; i++) begin : data_bank_gen
byte_en_BRAM #(CONFIG.DCACHE.LINES*CONFIG.DCACHE.LINE_W) data_bank (
byte_en_bram #(CONFIG.DCACHE.LINES*CONFIG.DCACHE.LINE_W) data_bank (
.clk(clk),
.addr_a(data_read_addr),
.addr_b(addr_utils.getDataLineAddr(stage2_store.addr)),

3
core/execution_units/load_store_unit/dcache_tag_banks.sv
View file

@ -90,9 +90,8 @@ module dcache_tag_banks
////////////////////////////////////////////////////
//Memory instantiation and hit detection
generate for (genvar i = 0; i < CONFIG.DCACHE.WAYS; i++) begin : tag_bank_gen
tag_bank #($bits(dtag_entry_t), CONFIG.DCACHE.LINES) dtag_bank (
dual_port_bram #(.WIDTH($bits(dtag_entry_t)), .LINES(CONFIG.DCACHE.LINES)) dtag_bank (
.clk (clk),
.rst (rst),
.en_a (store_req | (miss_req & miss_way[i]) | external_inv),
.wen_a ((miss_req & miss_way[i]) | external_inv),
.addr_a (porta_addr),

38
core/fetch_stage/branch_predictor.sv
View file

@ -104,31 +104,37 @@ module branch_predictor
genvar i;
generate if (CONFIG.INCLUDE_BRANCH_PREDICTOR)
for (i=0; i<CONFIG.BP.WAYS; i++) begin : gen_branch_tag_banks
branch_predictor_ram #(.C_DATA_WIDTH($bits(branch_table_entry_t)), .C_DEPTH(CONFIG.BP.ENTRIES))
dual_port_bram #(.WIDTH($bits(branch_table_entry_t)), .LINES(CONFIG.BP.ENTRIES))
tag_bank (
.clk (clk),
.rst (rst),
.write_addr (addr_utils.getHashedLineAddr(br_results.pc, i)),
.write_en (tag_update_way[i]),
.write_data (ex_entry),
.read_addr (addr_utils.getHashedLineAddr(bp.next_pc, i)),
.read_en (bp.new_mem_request),
.read_data (if_entry[i]));
.en_a (tag_update_way[i]),
.wen_a (tag_update_way[i]),
.addr_a (addr_utils.getHashedLineAddr(br_results.pc, i)),
.data_in_a (ex_entry),
.data_out_a (),
.en_b (bp.new_mem_request),
.wen_b (0),
.addr_b (addr_utils.getHashedLineAddr(bp.next_pc, i)),
.data_in_b ('0),
.data_out_b (if_entry[i]));
end
endgenerate
generate if (CONFIG.INCLUDE_BRANCH_PREDICTOR)
for (i=0; i<CONFIG.BP.WAYS; i++) begin : gen_branch_table_banks
branch_predictor_ram #(.C_DATA_WIDTH(32), .C_DEPTH(CONFIG.BP.ENTRIES))
dual_port_bram #(.WIDTH(32), .LINES(CONFIG.BP.ENTRIES))
addr_table (
.clk (clk),
.rst (rst),
.write_addr (addr_utils.getHashedLineAddr(br_results.pc, i)),
.write_en (target_update_way[i]),
.write_data (br_results.target_pc),
.read_addr (addr_utils.getHashedLineAddr(bp.next_pc, i)),
.read_en (bp.new_mem_request),
.read_data (predicted_pc[i])
.en_a (target_update_way[i]),
.wen_a (target_update_way[i]),
.addr_a (addr_utils.getHashedLineAddr(br_results.pc, i)),
.data_in_a (br_results.target_pc),
.data_out_a (),
.en_b (bp.new_mem_request),
.wen_b (0),
.addr_b (addr_utils.getHashedLineAddr(bp.next_pc, i)),
.data_in_b ('0),
.data_out_b (predicted_pc[i])
);
end
endgenerate

64
core/fetch_stage/branch_predictor_ram.sv
View file

@ -1,64 +0,0 @@
/*
* Copyright © 2019 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module branch_predictor_ram
import cva5_config::*;
import cva5_types::*;
#(
parameter C_DATA_WIDTH = 20,
parameter C_DEPTH = 512
)
(
input logic clk,
input logic rst,
input logic [$clog2(C_DEPTH)-1:0] write_addr,
input logic write_en,
input logic [$clog2(C_DEPTH)-1:0] read_addr,
input logic read_en,
input logic [C_DATA_WIDTH-1:0] write_data,
output logic [C_DATA_WIDTH-1:0] read_data
);
(* ram_style = "block" *)logic [C_DATA_WIDTH-1:0] branch_ram [C_DEPTH-1:0];
////////////////////////////////////////////////////
//Implementation
initial branch_ram = '{default: 0};
always_ff @(posedge clk) begin
if (write_en)
branch_ram[write_addr] <= write_data;
end
always_ff @(posedge clk) begin
if (read_en)
read_data <= branch_ram[read_addr];
end
////////////////////////////////////////////////////
//End of Implementation
////////////////////////////////////////////////////
////////////////////////////////////////////////////
//Assertions
////////////////////////////////////////////////////
//Trace Interface
endmodule

14
core/fetch_stage/icache.sv
View file

@ -190,17 +190,17 @@ module icache
//Data Banks
genvar i;
generate for (i=0; i < CONFIG.ICACHE.WAYS; i++) begin : idata_bank_gen
byte_en_BRAM #(CONFIG.ICACHE.LINES*CONFIG.ICACHE.LINE_W) idata_bank (
dual_port_bram #(.WIDTH(32), .LINES(CONFIG.ICACHE.LINES*CONFIG.ICACHE.LINE_W)) idata_bank (
.clk(clk),
.addr_a(addr_utils.getDataLineAddr(new_request_addr)),
.addr_b(addr_utils.getDataLineAddr({second_cycle_addr[31:SCONFIG.SUB_LINE_ADDR_W+2], word_count, 2'b0})),
.en_a(new_request),
.en_b(tag_update_way[i] & l1_response.data_valid),
.be_a('0),
.be_b('1),
.wen_a(0),
.addr_a(addr_utils.getDataLineAddr(new_request_addr)),
.data_in_a('0),
.data_in_b(l1_response.data),
.data_out_a(data_out[i]),
.en_b(1),
.wen_b(tag_update_way[i] & l1_response.data_valid),
.addr_b(addr_utils.getDataLineAddr({second_cycle_addr[31:SCONFIG.SUB_LINE_ADDR_W+2], word_count, 2'b0})),
.data_in_b(l1_response.data),
.data_out_b()
);
end endgenerate

3
core/fetch_stage/icache_tag_banks.sv
View file

@ -63,7 +63,8 @@ module itag_banks
genvar i;
generate
for (i=0; i < CONFIG.ICACHE.WAYS; i++) begin : tag_bank_gen
tag_bank #(SCONFIG.TAG_W+1, CONFIG.ICACHE.LINES) itag_bank (.*,
dual_port_bram #(.WIDTH(SCONFIG.TAG_W+1), .LINES(CONFIG.ICACHE.LINES)) itag_bank (.*,
.clk(clk),
.en_a(stage1_adv),
.wen_a('0),
.addr_a(stage1_line_addr),

2
examples/zedboard/cva5_wrapper.sv
View file

@ -243,7 +243,7 @@ module cva5_wrapper (
endgenerate
//arm proc(.*);
byte_en_BRAM #(MEM_LINES, "/home/ematthew/Research/RISCV/software2/riscv-tools/riscv-tests/benchmarks/fft.riscv.hw_init", 1) inst_data_ram (
byte_en_bram #(MEM_LINES, "/home/ematthew/Research/RISCV/software2/riscv-tools/riscv-tests/benchmarks/fft.riscv.hw_init", 1) inst_data_ram (
.clk(clk),
.addr_a(instruction_bram.addr[$clog2(MEM_LINES)- 1:0]),
.en_a(instruction_bram.en),

2
local_memory/local_mem.sv
View file

@ -36,7 +36,7 @@ module local_mem
localparam LINES = (RAM_SIZE/4)*1024; //RAM width is 32-bits, so for RAM_SIZE in KB, divide by 4 and multiply by 1024.
byte_en_BRAM #(LINES, preload_file, USE_PRELOAD_FILE) inst_data_ram (
byte_en_bram #(LINES, preload_file, USE_PRELOAD_FILE) inst_data_ram (
.clk(clk),
.addr_a(portA.addr[$clog2(LINES)- 1:0]),
.en_a(portA.en),

5
tools/compile_order
View file

@ -15,6 +15,7 @@ core/types_and_interfaces/external_interfaces.sv
core/common_components/lutram_1w_1r.sv
core/common_components/lutram_1w_mr.sv
core/common_components/dual_port_bram.sv
core/common_components/set_clr_reg_with_rst.sv
core/common_components/one_hot_to_integer.sv
core/common_components/cycler.sv
@ -26,7 +27,7 @@ core/common_components/toggle_memory_set.sv
core/common_components/vendor_support/intel/intel_byte_enable_ram.sv
core/common_components/vendor_support/xilinx/xilinx_byte_enable_ram.sv
core/common_components/byte_en_BRAM.sv
core/common_components/byte_en_bram.sv
core/execution_units/csr_unit.sv
core/execution_units/gc_unit.sv
@ -59,9 +60,7 @@ core/execution_units/div_core.sv
core/execution_units/div_unit.sv
core/fetch_stage/ras.sv
core/fetch_stage/branch_predictor_ram.sv
core/fetch_stage/branch_predictor.sv
core/fetch_stage/tag_bank.sv
core/fetch_stage/icache_tag_banks.sv
core/fetch_stage/icache.sv
core/fetch_stage/fetch.sv