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Intel inferrence changes

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This commit is contained in:
Eric Matthews 2021-04-03 14:33:45 -07:00
parent 5141043054
commit 18ef3699aa
1 changed files with 4 additions and 4 deletions
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8
core/register_bank.sv
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@ -55,10 +55,10 @@ module register_bank
if (commit)
register_file_bank[write_addr] <= new_data;
end
always_comb begin
foreach(read_addr[i])
data[i] = register_file_bank[read_addr[i]];
end
generate for (genvar i = 0; i < NUM_READ_PORTS; i++)
assign data[i] = register_file_bank[read_addr[i]];
endgenerate
////////////////////////////////////////////////////
//Assertions