github-mirrors/cva5
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva5.git synced 2025-04-20 12:07:53 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

FIFO cleanups

Browse source
This commit is contained in:
Eric Matthews 2019-08-20 22:07:53 -07:00
parent 306a868d1d
commit 1a548616b4
6 changed files with 87 additions and 88 deletions
Download patch file Download diff file Expand all files Collapse all files

99
core/binary_occupancy.sv
View file

@ -1,5 +1,5 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
* Copyright © 2017-2019 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -29,71 +29,77 @@ module binary_occupancy #(parameter DEPTH = 4)
input logic rst,
input logic push,
input logic pop,
output logic early_full,
output logic almost_full,
output logic full,
output logic empty,
output logic valid,
output logic early_valid,
output logic two_plus
output logic almost_empty,
output logic valid
);
logic[$clog2(DEPTH)-1:0] count;
//Occupancy Tracking
always_ff @ (posedge clk) begin
if (rst)
count <= 0;
else if (push & ~pop)
count <= count + 1;
else if (pop & ~push)
count <= count - 1;
else begin
case ({push, pop})
2'b10: count <= count + 1;
2'b01: count <= count - 1;
default : count <= count;
endcase
end
end
always_ff @ (posedge clk) begin
if (rst)
valid <= 0;
else if (push)
valid <= 1;
else if (pop && (count == 1))
valid <= 0;
else begin
case ({push, pop})
2'b10: valid <= 1;
2'b01: valid <= !(count == 1);
default : valid <= valid;
endcase
end
end
always_ff @ (posedge clk) begin
if (rst)
full <= 0;
else if ((push & ~pop) && (count == DEPTH-1))
full <= 1;
else if (pop)
full <= 0;
end
// always_ff @ (posedge clk) begin
// if (rst)
// full <= 0;
// else begin
// case ({push, pop})
// 2'b10: full <= (count == DEPTH-2);
// 2'b01: full <= 0;
// default : full <= full;
// endcase
// end
// end
always_ff @ (posedge clk) begin
if (rst)
early_full <= 0;
else if ((push & ~pop) && (count == DEPTH-2))
early_full <= 1;
else if (pop && (count == DEPTH-1))
early_full <= 0;
end
// always_ff @ (posedge clk) begin
// if (rst)
// almost_full <= 0;
// else begin
// case ({push, pop})
// 2'b10: almost_full <= (count == DEPTH-3);
// 2'b01: almost_full <= (count == DEPTH-1);
// default : almost_full <= almost_full;
// endcase
// end
// end
always_ff @ (posedge clk) begin
if (rst)
two_plus <= 0;
else if ((push & ~pop) && (count >= 1))
two_plus <= 1;
else if (pop && (count == 2))
two_plus <= 0;
end
// always_ff @ (posedge clk) begin
// if (rst)
// almost_empty <= 0;
// else begin
// case ({push, pop})
// 2'b10: almost_empty <=(count == 0);
// 2'b01: almost_empty <= (count == 2);
// default : almost_empty <= almost_empty;
// endcase
// end
// end
assign empty = ~valid;//(count == 0);
//assign valid = //(count != 0);
//assign full = (count == (DEPTH-1));
//assign early_full = (count == (DEPTH-2)) & push & ~pop;
//pushing, or more than one, or at least one and not popping
//assign two_plus = (count > 1);
assign early_valid = push | (two_plus) | (valid & ~pop);
assign empty = ~valid;
////////////////////////////////////////////////////
//Assertions
@ -102,7 +108,6 @@ module binary_occupancy #(parameter DEPTH = 4)
assert (!(~rst & empty & pop)) else $error("underflow");
end
endmodule

1
core/instruction_buffer.sv
View file

@ -49,7 +49,6 @@ module instruction_buffer
assign ib.valid = ib_fifo.valid;
assign ib.full = ib_fifo.full;
assign ib.early_full = ib_fifo.early_full;
taiga_fifo #(
.DATA_WIDTH($bits(instruction_buffer_packet)),

16
core/interfaces.sv
View file

@ -170,10 +170,9 @@ interface instruction_buffer_interface;
instruction_buffer_packet data_out;
logic valid;
logic full;
logic early_full;
modport buffer (input push, pop, flush, data_in, output data_out, valid, full, early_full);
modport fetch (input full, early_full, pop, output push, data_in, flush);
modport buffer (input push, pop, flush, data_in, output data_out, valid, full);
modport fetch (input full, pop, output push, data_in, flush);
modport decode (input valid, data_out, output pop);
//modport exception_control (output flush);
endinterface
@ -187,12 +186,11 @@ interface fifo_interface #(parameter DATA_WIDTH = 42);//#(parameter type data_ty
logic valid;
logic full;
logic empty;
logic early_full;
logic early_valid;
logic early_empty;
modport enqueue (input early_full, full, empty, output data_in, push);
modport dequeue (input early_valid, valid, early_empty, data_out, output pop);
modport structure(input push, pop, data_in, output data_out, early_valid, valid, early_full, full, empty, early_empty);
logic almost_full;//full minus 1
logic almost_empty;//only one entry
modport enqueue (input almost_full, full, empty, output data_in, push);
modport dequeue (input valid, almost_empty, data_out, output pop);
modport structure(input push, pop, data_in, output data_out, valid, almost_full, full, empty, almost_empty);
endinterface
interface mmu_interface;

2
core/load_store_unit.sv
View file

@ -124,7 +124,7 @@ module load_store_unit (
assign input_fifo.push = ls_ex.new_request_dec;
assign ls_ex.ready = (LS_INPUT_BUFFER_DEPTH >= MAX_INFLIGHT_COUNT) ? 1 : ~input_fifo.full;
assign input_fifo.pop = issue_request | gc_issue_flush;
assign load_store_FIFO_emptying = input_fifo.early_empty;
assign load_store_FIFO_emptying = input_fifo.almost_empty & issue_request & ~ls_ex.new_request_dec;
assign stage1 = input_fifo.data_out;
////////////////////////////////////////////////////

26
core/one_hot_occupancy.sv
View file

@ -1,5 +1,5 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
* Copyright © 2017-2019 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -29,16 +29,15 @@ module one_hot_occupancy #(parameter DEPTH = 4)
input logic rst,
input logic push,
input logic pop,
output logic early_full,
output logic almost_full,
output logic full,
output logic empty,
output logic early_empty,
output logic almost_empty,
output logic valid,
output logic early_valid,
output logic two_plus
);
logic[DEPTH:0] valid_chain;
logic [DEPTH:0] valid_chain;
//Occupancy Tracking
always_ff @ (posedge clk) begin
@ -48,25 +47,20 @@ module one_hot_occupancy #(parameter DEPTH = 4)
end
else begin
case({push,pop})
0 : valid_chain <= valid_chain;
1 : valid_chain <= {1'b0, valid_chain[DEPTH:1]};
2 : valid_chain <= {valid_chain[DEPTH-1:0], 1'b0};
3 : valid_chain <= valid_chain;
2'b10 : valid_chain <= {valid_chain[DEPTH-1:0], 1'b0};
2'b01 : valid_chain <= {1'b0, valid_chain[DEPTH:1]};
default : valid_chain <= valid_chain;
endcase
end
end
assign empty = valid_chain[0];
assign early_empty = valid_chain[1] & pop & ~push;
assign almost_empty = valid_chain[1];
assign valid = ~valid_chain[0];
assign full = valid_chain[DEPTH];
assign early_full = valid_chain[DEPTH-1] | valid_chain[DEPTH];
//pushing, or more than one, or at least one and not popping
assign two_plus = ~valid_chain[0] & ~valid_chain[1];
assign early_valid = push | (two_plus) | (valid & ~pop);
assign almost_full = valid_chain[DEPTH-1];
////////////////////////////////////////////////////
//Assertions
@ -75,4 +69,4 @@ module one_hot_occupancy #(parameter DEPTH = 4)
assert (!(~rst & valid_chain[0] & pop)) else $error("underflow");
end
endmodule
endmodule

31
core/taiga_fifo.sv
View file

@ -1,5 +1,5 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
* Copyright © 2017-2019 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -26,6 +26,7 @@ import taiga_types::*;
/*
* FIFOs Not underflow/overflow safe.
* Intended for small FIFO depths.
* For continuous operation when full, enqueing side must inspect pop signal
*/
module taiga_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, parameter fifo_type_t FIFO_TYPE = NON_MUXED_INPUT_FIFO)
(
@ -48,12 +49,17 @@ module taiga_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, paramet
//implementation
////////////////////////////////////////////////////
generate if (FIFO_DEPTH == 1) begin
one_hot_occupancy #(.DEPTH(FIFO_DEPTH)) occupancy_tracking
(
.push(fifo.push), .pop(fifo.pop),
.early_full(fifo.early_full), .full(fifo.full),
.empty(fifo.empty), .early_empty(fifo.early_empty), .valid(fifo.valid), .early_valid(fifo.early_valid), .two_plus(two_plus), .*
);
always_ff @ (posedge clk) begin
if (rst)
fifo.valid <= 0;
else if (fifo.push)
fifo.valid <= 1;
else if (fifo.pop)
fifo.valid <= 0;
end
assign fifo.full = fifo.valid;
assign fifo.empty = ~fifo.valid;
always_ff @ (posedge clk) begin
if (fifo.push)
fifo.data_out <= fifo.data_in;
@ -68,8 +74,8 @@ module taiga_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, paramet
one_hot_occupancy #(.DEPTH(FIFO_DEPTH)) occupancy_tracking
(
.push(fifo.push), .pop(fifo.pop),
.early_full(fifo.early_full), .full(fifo.full),
.empty(fifo.empty), .early_empty(fifo.early_empty), .valid(fifo.valid), .early_valid(fifo.early_valid), .two_plus(two_plus), .*
.almost_full(fifo.almost_full), .full(fifo.full),
.empty(fifo.empty), .almost_empty(fifo.almost_empty), .valid(fifo.valid), .*
);
always_ff @ (posedge clk) begin
@ -103,7 +109,6 @@ module taiga_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, paramet
logic [SRL_DEPTH_W-1:0] srl_index;
logic full;
logic full_minus_one;
logic more_than_one;
logic one_entry;
//On first write will roll over to [1,00...0]
@ -119,7 +124,6 @@ module taiga_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, paramet
//Helper expressions
assign full = fifo.valid && (srl_index[SRL_DEPTH_W-2:0] == (FIFO_DEPTH-1));
assign full_minus_one = fifo.valid && (srl_index[SRL_DEPTH_W-2:0] == (FIFO_DEPTH-2));
assign more_than_one = fifo.valid && (srl_index[SRL_DEPTH_W-2:0] != 0);
assign one_entry = fifo.valid && (srl_index[SRL_DEPTH_W-2:0] == 0);
assign fifo.valid = srl_index[SRL_DEPTH_W-1];
@ -129,9 +133,8 @@ module taiga_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, paramet
fifo.full = ~fifo.pop & ((fifo.push & full_minus_one) | full);
end
assign fifo.early_valid = fifo.push | (fifo.valid & ~fifo.pop) | more_than_one;
assign fifo.early_empty = one_entry & fifo.pop & ~fifo.push;
assign fifo.early_full = fifo.full | (full_minus_one & fifo.push);
assign fifo.almost_empty = one_entry;
assign fifo.almost_full = full_minus_one;
always_ff @ (posedge clk) begin
if (fifo.push)