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Fix AXI support for independent icache/dcache line widths

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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews 2022-05-16 16:48:10 -04:00
parent b4d6a9fa29
commit 207c47abd7
1 changed files with 1 additions and 1 deletions
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core/axi_to_arb.sv
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@ -166,7 +166,7 @@ module axi_to_arb
assign axi_arprot = '0;
assign axi_arid = 6'(l2.id);
assign axi_araddr ={l2.addr[29:$clog2(EXAMPLE_CONFIG.DCACHE.LINE_W)], {$clog2(EXAMPLE_CONFIG.DCACHE.LINE_W){1'b0}}, 2'b00};
assign axi_araddr ={l2.addr, 2'b00} & {25'h1FFFFFF, ~burst_count, 2'b00};
assign write_reference_burst_count = read_modify_write ? 0 : burst_count;