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change some naming in the litex wrapper and fixing hte tlb depth
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msa417
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1 changed files with 81 additions and 102 deletions
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@ -41,6 +41,7 @@ module litex_wrapper
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input logic [NUM_CORES-1:0] msip,
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input logic [63:0] mtime,
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//Wishbone memory port (used only if configured)
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output logic [29:0] idbus_adr,
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output logic [31:0] idbus_dat_w,
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output logic [3:0] idbus_sel,
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@ -53,51 +54,43 @@ module litex_wrapper
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input logic idbus_ack,
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input logic idbus_err,
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// AXI SIGNALS - need these to unwrap the interface for packaging //
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input logic m_axi_arready,
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output logic m_axi_arvalid,
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output logic [32-1:0] m_axi_araddr,
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output logic [7:0] m_axi_arlen,
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output logic [2:0] m_axi_arsize,
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output logic [1:0] m_axi_arburst,
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output logic [3:0] m_axi_arcache,
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output logic [5:0] m_axi_arid,
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//read data
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output logic m_axi_rready,
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input logic m_axi_rvalid,
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input logic [32-1:0] m_axi_rdata,
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input logic [1:0] m_axi_rresp,
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input logic m_axi_rlast,
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input logic [5:0] m_axi_rid,
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//Write channel
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//write address
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input logic m_axi_awready,
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output logic m_axi_awvalid,
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output logic [32-1:0] m_axi_awaddr,
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output logic [7:0] m_axi_awlen,
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output logic [2:0] m_axi_awsize,
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output logic [1:0] m_axi_awburst,
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output logic [3:0] m_axi_awcache,
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output logic [5:0] m_axi_awid,
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//write data
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input logic m_axi_wready,
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output logic m_axi_wvalid,
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output logic [32-1:0] m_axi_wdata,
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output logic [(32/8)-1:0] m_axi_wstrb,
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output logic m_axi_wlast,
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//write response
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output logic m_axi_bready,
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input logic m_axi_bvalid,
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input logic [1:0] m_axi_bresp,
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input logic [5:0] m_axi_bid
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//AXI memory port (used only if configured)
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//AR
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input logic m_axi_arready,
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output logic m_axi_arvalid,
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output logic [31:0] m_axi_araddr,
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output logic [7:0] m_axi_arlen,
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output logic [2:0] m_axi_arsize, //Constant, 32b
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output logic [1:0] m_axi_arburst, //Constant, incrementing
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output logic [3:0] m_axi_arcache, //Constant, normal non-cacheable bufferable
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output logic [5:0] m_axi_arid,
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//R
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output logic m_axi_rready,
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input logic m_axi_rvalid,
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input logic [31:0] m_axi_rdata,
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input logic [1:0] m_axi_rresp,
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input logic m_axi_rlast,
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input logic [5:0] m_axi_rid,
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//AW
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input logic m_axi_awready,
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output logic m_axi_awvalid,
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output logic [31:0] m_axi_awaddr,
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output logic [7:0] m_axi_awlen, //Constant, 0
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output logic [2:0] m_axi_awsize, //Constant, 32b
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output logic [1:0] m_axi_awburst, //Constant, incrementing
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output logic [3:0] m_axi_awcache, //Constant, normal non-cacheable bufferable
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output logic [5:0] m_axi_awid,
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//W
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input logic m_axi_wready,
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output logic m_axi_wvalid,
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output logic [31:0] m_axi_wdata,
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output logic [3:0] m_axi_wstrb,
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output logic m_axi_wlast,
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//B
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output logic m_axi_bready,
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input logic m_axi_bvalid,
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input logic [1:0] m_axi_bresp,
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input logic [5:0] m_axi_bid
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);
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localparam wb_group_config_t STANDARD_WB_GROUP_CONFIG = '{
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@ -108,8 +101,8 @@ module litex_wrapper
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};
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//Unused interfaces
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axi_interface m_axi[NUM_CORES-1:0]();
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avalon_interface m_avalon[NUM_CORES-1:0]();
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axi_interface axi[NUM_CORES-1:0]();
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avalon_interface avalon[NUM_CORES-1:0]();
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wishbone_interface dwishbone[NUM_CORES-1:0]();
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wishbone_interface iwishbone[NUM_CORES-1:0]();
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local_memory_interface instruction_bram[NUM_CORES-1:0]();
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@ -121,10 +114,7 @@ module litex_wrapper
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//Memory interfaces for each core
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mem_interface mem[NUM_CORES-1:0]();
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//Final memory interface
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generate for (genvar i = 0; i < NUM_CORES; i++) begin : gen_cores
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localparam cpu_config_t STANDARD_CONFIG_I = '{
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//ISA options
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@ -177,7 +167,7 @@ module litex_wrapper
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},
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ITLB : '{
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WAYS : 2,
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DEPTH : 2
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DEPTH : 64
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},
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INCLUDE_DCACHE : 1,
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DCACHE_ADDR : '{
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@ -197,7 +187,7 @@ module litex_wrapper
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},
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DTLB : '{
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WAYS : 2,
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DEPTH : 2
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DEPTH : 64
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},
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INCLUDE_ILOCAL_MEM : 0,
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ILOCAL_MEM_ADDR : '{
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@ -242,8 +232,8 @@ module litex_wrapper
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cva5 #(.CONFIG(STANDARD_CONFIG_I)) cpu(
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.instruction_bram(instruction_bram[i]),
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.data_bram(data_bram[i]),
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.m_axi(m_axi[i]),
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.m_avalon(m_avalon[i]),
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.m_axi(axi[i]),
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.m_avalon(avalon[i]),
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.dwishbone(dwishbone[i]),
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.iwishbone(iwishbone[i]),
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.mem(mem[i]),
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@ -252,62 +242,55 @@ module litex_wrapper
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.m_interrupt(m_interrupt[i]),
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.*);
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end endgenerate
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//Final memory interface
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generate if (AXI) begin : gen_axi_if
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axi_interface m_axi_l2();
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axi_interface m_axi();
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axi_adapter #(.NUM_CORES(NUM_CORES)) wb_adapter (
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//Mux requests from one or more cores onto the AXI bus
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axi_adapter #(.NUM_CORES(NUM_CORES)) axi_adapter (
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.mems(mem),
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.axi(m_axi_l2),
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.axi(m_axi),
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.*);
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assign m_axi.arready = m_axi_arready;
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assign m_axi_arvalid = m_axi.arvalid;
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assign m_axi_araddr = m_axi.araddr;
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assign m_axi_arlen = m_axi.arlen;
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assign m_axi_arsize = m_axi.arsize;
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assign m_axi_arburst = m_axi.arburst;
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assign m_axi_arcache = m_axi.arcache;
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assign m_axi_arid = m_axi.arid;
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assign m_axi_l2.arready = m_axi_arready ;
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assign m_axi_arvalid = m_axi_l2.arvalid;
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assign m_axi_araddr = m_axi_l2.araddr;
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assign m_axi_arlen = m_axi_l2.arlen;
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assign m_axi_arsize = m_axi_l2.arsize;
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assign m_axi_arburst = m_axi_l2.arburst;
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assign m_axi_arcache = m_axi_l2.arcache;
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assign m_axi_arid = m_axi_l2.arid;
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assign m_axi_rready = m_axi.rready;
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assign m_axi.rvalid = m_axi_rvalid;
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assign m_axi.rdata = m_axi_rdata;
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assign m_axi.rresp = m_axi_rresp;
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assign m_axi.rlast = m_axi_rlast;
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assign m_axi.rid = m_axi_rid;
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assign m_axi_rready = m_axi_l2.rready;
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assign m_axi_l2.rvalid = m_axi_rvalid;
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assign m_axi_l2.rdata = m_axi_rdata;
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assign m_axi_l2.rresp = m_axi_rresp;
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assign m_axi_l2.rlast = m_axi_rlast;
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assign m_axi_l2.rid = m_axi_rid;
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assign m_axi_l2.awready = m_axi_awready;
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assign m_axi_awvalid = m_axi_l2.awvalid;
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assign m_axi_awaddr = m_axi_l2.awaddr;
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assign m_axi_awlen = m_axi_l2.awlen;
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assign m_axi_awsize = m_axi_l2.awsize;
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assign m_axi_awburst = m_axi_l2.awburst;
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assign m_axi_awcache = m_axi_l2.awcache;
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assign m_axi_awid = m_axi_l2.awid;
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//write data
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assign m_axi_l2.wready = m_axi_wready;
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assign m_axi_wvalid = m_axi_l2.wvalid;
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assign m_axi_wdata = m_axi_l2.wdata;
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assign m_axi_wstrb = m_axi_l2.wstrb;
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assign m_axi_wlast = m_axi_l2.wlast;
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//write response
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assign m_axi_bready = m_axi_l2.bready;
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assign m_axi_l2.bvalid = m_axi_bvalid;
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assign m_axi_l2.bresp = m_axi_bresp;
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assign m_axi_l2.bid = m_axi_bid;
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assign m_axi.awready = m_axi_awready;
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assign m_axi_awvalid = m_axi.awvalid;
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assign m_axi_awaddr = m_axi.awaddr;
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assign m_axi_awlen = m_axi.awlen;
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assign m_axi_awsize = m_axi.awsize;
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assign m_axi_awburst = m_axi.awburst;
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assign m_axi_awcache = m_axi.awcache;
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assign m_axi_awid = m_axi.awid;
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assign m_axi.wready = m_axi_wready;
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assign m_axi_wvalid = m_axi.wvalid;
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assign m_axi_wdata = m_axi.wdata;
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assign m_axi_wstrb = m_axi.wstrb;
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assign m_axi_wlast = m_axi.wlast;
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assign m_axi_bready = m_axi.bready;
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assign m_axi.bvalid = m_axi_bvalid;
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assign m_axi.bresp = m_axi_bresp;
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assign m_axi.bid = m_axi_bid;
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end else begin : gen_wishbone_if
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wishbone_interface idwishbone();
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//Mux requests from one or more cores onto the wishbone bus
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@ -329,8 +312,4 @@ module litex_wrapper
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assign idwishbone.err = idbus_err;
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end endgenerate
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endmodule
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