added missing Intel LUTRAM attributes

core/csr_regs.sv

@@ -80,7 +80,7 @@ module csr_regs (
     logic [1:0] privilege_level, next_privilege_level;
 
     //scratch ram
-    logic[XLEN-1:0] scratch_regs [31:0];//Only 0x1 and 0x3 used by supervisor and machine mode respectively
+    (* ramstyle = "MLAB, no_rw_check" *) logic[XLEN-1:0] scratch_regs [31:0];//Only 0x1 and 0x3 used by supervisor and machine mode respectively
     logic[XLEN-1:0] scratch_out;
 
 

core/decode.sv

@@ -82,7 +82,7 @@ module decode(
 
     logic nop;
 
-    logic  register_in_use_by_load_op [31:0];
+    (* ramstyle = "MLAB, no_rw_check" *) logic  register_in_use_by_load_op [31:0];
 
     logic store_data_in_use_by_load_op;
     logic load_store_forward_possible;

core/ras.sv

@@ -29,12 +29,12 @@ module ras (
         ras_interface.self ras
         );
 
-    logic[31:0] lut_ram [RAS_DEPTH-1:0];
+    (* ramstyle = "MLAB, no_rw_check" *) logic[31:0] lut_ram [RAS_DEPTH-1:0];
 
     localparam RAS_DEPTH_W = $clog2(RAS_DEPTH);
     logic[RAS_DEPTH_W-1:0] read_index;
     logic[RAS_DEPTH_W-1:0] write_index;
-    logic valid_chain[RAS_DEPTH-1:0];
+    (* ramstyle = "MLAB, no_rw_check" *) logic valid_chain[RAS_DEPTH-1:0];
     logic valid_chain_update;
     ///////////////////////////////////////////////////////
     //For simulation purposes

core/write_back.sv

@@ -42,7 +42,7 @@ module write_back(
     //////////////////////////////////////
 
     //Inflight packetscd
-    logic[$bits(inflight_instruction_packet)-1:0] packet_table [MAX_INFLIGHT_COUNT-1:0];
+    (* ramstyle = "MLAB, no_rw_check" *) logic[$bits(inflight_instruction_packet)-1:0] packet_table [MAX_INFLIGHT_COUNT-1:0];
 
     //aliases for write-back-interface signals
     instruction_id_t unit_instruction_id [NUM_WB_UNITS-1:0];