FIFO reg bypass for fetch buffer and tracing updates

core/branch_unit.sv

@@ -179,7 +179,10 @@ module branch_unit(
 
     ////////////////////////////////////////////////////
     //Trace Interface
-    assign tr_branch_misspredict = ~is_return & miss_predict;
-    assign tr_return_misspredict = is_return & miss_predict;
+    generate if (ENABLE_TRACE_INTERFACE) begin
+        assign tr_branch_misspredict = ~is_return & miss_predict;
+        assign tr_return_misspredict = is_return & miss_predict;
+    end
+    endgenerate
 
 endmodule

core/decode.sv

@@ -50,6 +50,7 @@ module decode(
 
         output logic load_store_issue,
 
+        output logic instruction_issued,
         output logic instruction_issued_no_rd,
         output logic instruction_issued_with_rd,
         output logic illegal_instruction,
@@ -97,7 +98,6 @@ module decode(
     logic [NUM_UNITS-1:0] issue_ready;
     logic [NUM_UNITS-1:0] issue;
 
-    logic instruction_issued;
     logic valid_opcode;
 
     //LS-inputs
@@ -432,15 +432,17 @@ module decode(
 
     ////////////////////////////////////////////////////
     //Trace Interface
-    assign tr_operand_stall = (|issue_ready) & issue_valid & ~load_store_operands_ready;
-    assign tr_unit_stall = ~(|issue_ready) & issue_valid & load_store_operands_ready;
-    assign tr_no_id_stall = (|issue_ready) & (fb_valid & ~ti.id_available & ~gc_issue_hold & ~gc_fetch_flush) & load_store_operands_ready;
-    assign tr_no_instruction_stall = ~fb_valid;
-    assign tr_other_stall = fb_valid & ~instruction_issued & ~(tr_operand_stall | tr_unit_stall | tr_no_id_stall | tr_no_instruction_stall) & ~gc_fetch_flush;
-
-    assign tr_instruction_issued_dec = instruction_issued;
-    assign tr_instruction_pc_dec = fb.pc;
-    assign tr_instruction_data_dec = fb.instruction;
+    generate if (ENABLE_TRACE_INTERFACE) begin
+        assign tr_operand_stall = (|issue_ready) & issue_valid & ~load_store_operands_ready;
+        assign tr_unit_stall = ~(|issue_ready) & issue_valid & load_store_operands_ready;
+        assign tr_no_id_stall = (|issue_ready) & (fb_valid & ~ti.id_available & ~gc_issue_hold & ~gc_fetch_flush) & load_store_operands_ready;
+        assign tr_no_instruction_stall = ~fb_valid;
+        assign tr_other_stall = fb_valid & ~instruction_issued & ~(tr_operand_stall | tr_unit_stall | tr_no_id_stall | tr_no_instruction_stall) & ~gc_fetch_flush;
 
+        assign tr_instruction_issued_dec = instruction_issued;
+        assign tr_instruction_pc_dec = fb.pc;
+        assign tr_instruction_data_dec = fb.instruction;
+    end
+    endgenerate
 
 endmodule

core/pre_decode.sv

@@ -60,7 +60,10 @@ module pre_decode
 
     logic rs1_link, rd_link, rs1_eq_rd, use_ras;
 
+    logic bypass_condition;
+
     fetch_buffer_packet_t data_in;
+    fetch_buffer_packet_t data_out;
     fifo_interface #(.DATA_WIDTH($bits(fetch_buffer_packet_t))) fb_fifo();
 
     ////////////////////////////////////////////////////
@@ -68,11 +71,29 @@ module pre_decode
     //FIFO
     assign buffer_reset = rst | gc_fetch_flush;
 
-    assign fb_fifo.push = pre_decode_push;
-    assign fb_fifo.pop = pre_decode_pop;
+    assign fb_fifo.push = pre_decode_push & ~bypass_condition;
+    assign fb_fifo.pop = pre_decode_pop & fb_fifo.valid;
     assign fb_fifo.data_in = data_in;
-    assign fb = fb_fifo.data_out;
-    assign fb_valid = fb_fifo.valid;
+    assign data_out = fb_fifo.data_out;
+
+    assign bypass_condition = fb_fifo.empty & (~fb_valid | (fb_valid & pre_decode_pop));
+
+    //Bypass overrides
+    always_ff @ (posedge clk) begin
+        if (pre_decode_push & bypass_condition)
+            fb <= data_in;
+        else if (pre_decode_pop)
+            fb <= data_out;
+    end
+
+    always_ff @ (posedge clk) begin
+        if (buffer_reset)
+            fb_valid <= 0;
+        else if (pre_decode_push)
+            fb_valid <= 1;
+        else if (pre_decode_pop & fb_fifo.empty)
+            fb_valid <= 0;
+    end
 
     taiga_fifo #(
             .DATA_WIDTH($bits(fetch_buffer_packet_t)),

core/register_file.sv

@@ -28,6 +28,8 @@ module register_file(
         input logic rst,
         input logic inuse_clear,
         input logic gc_supress_writeback,
+
+        input logic instruction_issued,
         register_file_writeback_interface.unit rf_wb,
         register_file_decode_interface.unit rf_decode,
 
@@ -116,8 +118,11 @@ module register_file(
 
     ////////////////////////////////////////////////////
     //Trace Interface
-    assign tr_rs1_forwarding_needed = rs1_inuse & rf_decode.uses_rs1 & ~tr_rs1_and_rs2_forwarding_needed;
-    assign tr_rs2_forwarding_needed = rs2_inuse & rf_decode.uses_rs2 & ~tr_rs1_and_rs2_forwarding_needed;
-    assign tr_rs1_and_rs2_forwarding_needed = (rs1_inuse & rf_decode.uses_rs1) & (rs2_inuse & rf_decode.uses_rs2);
+    generate if (ENABLE_TRACE_INTERFACE) begin
+        assign tr_rs1_forwarding_needed = instruction_issued & rs1_inuse & rf_decode.uses_rs1 & ~tr_rs1_and_rs2_forwarding_needed;
+        assign tr_rs2_forwarding_needed = instruction_issued & rs2_inuse & rf_decode.uses_rs2 & ~tr_rs1_and_rs2_forwarding_needed;
+        assign tr_rs1_and_rs2_forwarding_needed = instruction_issued & (rs1_inuse & rf_decode.uses_rs1) & (rs2_inuse & rf_decode.uses_rs2);
+    end
+    endgenerate
 
 endmodule

core/taiga.sv

@@ -109,6 +109,7 @@ module taiga (
     logic illegal_instruction;
     logic instruction_queue_empty;
 
+    logic instruction_issued;
     logic instruction_issued_no_rd;
     logic instruction_issued_with_rd;
     logic instruction_complete;