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Switch L1 arbitration to round-robin

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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews 2022-11-14 13:15:12 -05:00
parent 4d42d3445d
commit 3e691efb37
2 changed files with 22 additions and 9 deletions
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4
core/cva5_config.sv
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@ -309,8 +309,8 @@ package cva5_config;
localparam L1_CONNECTIONS = 4;
typedef enum bit [1:0] {
L1_DCACHE_ID = 0,
L1_DMMU_ID = 1,
L1_ICACHE_ID = 2,
L1_ICACHE_ID = 1,
L1_DMMU_ID = 2,
L1_IMMU_ID = 3
} l1_id_t;

27
core/l1_arbiter.sv
View file

@ -76,7 +76,7 @@ module l1_arbiter
////////////////////////////////////////////////////
//Dcache Specific
assign l2.wr_data_push = CONFIG.INCLUDE_DCACHE & (l1_request[L1_DCACHE_ID].request & ~l1_request[L1_DCACHE_ID].rnw & ~fifos_full); //Assumes data cache has highest priority
assign l2.wr_data_push = l2.request_push & ~l2.rnw;
assign l2.wr_data = l1_request[L1_DCACHE_ID].data;
assign l2.inv_ack = CONFIG.DCACHE.USE_EXTERNAL_INVALIDATIONS ? l1_response[L1_DCACHE_ID].inv_ack : l2.inv_valid;
@ -98,12 +98,25 @@ module l1_arbiter
////////////////////////////////////////////////////
//Arbitration
priority_encoder #(.WIDTH(L1_CONNECTIONS))
arb_encoder
(
.priority_vector (requests),
.encoded_result (arb_sel)
);
logic [$clog2(L1_CONNECTIONS)-1:0] state;
logic [$clog2(L1_CONNECTIONS)-1:0] muxes [L1_CONNECTIONS-1:0];
always_ff @(posedge clk) begin
if (rst)
state <= 0;
else if (l2.request_push)
state <= arb_sel;
end
always_comb begin
for (int i = 0; i < L1_CONNECTIONS; i++) begin
muxes[i] = $clog2(L1_CONNECTIONS)'(i);
for (int j = 0; j < L1_CONNECTIONS; j++) begin
if (requests[(i + j) % L1_CONNECTIONS])
muxes[i] = $clog2(L1_CONNECTIONS)'((i + j) % L1_CONNECTIONS);
end
end
end
assign arb_sel = muxes[state];
assign acks = L1_CONNECTIONS'(l2.request_push) << arb_sel;