id tracking updates and barrel shifter update

core/barrel_shifter.sv

@@ -37,39 +37,42 @@ module barrel_shifter (
     //Bit flipping shared shifter
     always_comb begin
         foreach (shifter_input[i])
-            preshifted_input[i] = lshift ? shifter_input[XLEN-i-1] : shifter_input[i];
+            preshifted_input[i] = shifter_input[31-i];
+    end
+
+    always_comb begin//2
+        case ({lshift, shift_amount[0]})
+            0: shiftx1 = shifter_input[31:0];
+            1: shiftx1 = {{1{arith}},shifter_input[31:1]};
+            2: shiftx1 = preshifted_input[31:0];
+            3: shiftx1 = {{1{arith}},preshifted_input[31:1]};
+        endcase
+    end
+
+        always_comb begin//2
+        case (shift_amount[2:1])
+            0: shiftx2 = shiftx1[31:0];
+            1: shiftx2 = {{2{arith}},shiftx1[31:2]};
+            2: shiftx2 = {{4{arith}},shiftx1[31:4]};
+            3: shiftx2 = {{6{arith}},shiftx1[31:6]};
+        endcase
     end
 
     always_comb begin//8
         case (shift_amount[4:3])
-            0: shiftx8 = preshifted_input;
-            1: shiftx8 = {{8{arith}}, preshifted_input[31:8]};
-            2: shiftx8 = {{16{arith}}, preshifted_input[31:16]};
-            3: shiftx8 =  {{24{arith}}, preshifted_input[31:24]};
-        endcase
-    end
-
-    always_comb begin//2
-        case (shift_amount[2:1])
-            0: shiftx2 = shiftx8[31:0];
-            1: shiftx2 = {{2{arith}},shiftx8[31:2]};
-            2: shiftx2 = {{4{arith}},shiftx8[31:4]};
-            3: shiftx2 = {{6{arith}},shiftx8[31:6]};
+            0: shiftx8 = shiftx2[31:0];
+            1: shiftx8 = {{8{arith}},shiftx2[31:8]};
+            2: shiftx8 = {{16{arith}},shiftx2[31:16]};
+            3: shiftx8 = {{24{arith}},shiftx2[31:24]};
         endcase
     end
+    assign shifted_resultr = shiftx8;
 
     always_comb begin
-        case (shift_amount[0])
-            0: shiftx1 = shiftx2[31:0];
-            1: shiftx1 = {arith,shiftx2[31:1]};
-        endcase
+        foreach (shifter_input[i])
+            shifted_resultl[i] = shiftx8[31-i];
     end
 
-   assign shifted_resultr = shiftx1;
-   always_comb begin
-       foreach (shiftx1[i]) shifted_resultl[i] = shiftx1[31-i];
-   end
-
 endmodule
 
 

core/id_inuse.sv

@@ -0,0 +1,93 @@
+/*
+ * Copyright © 2019 Eric Matthews,  Lesley Shannon
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Initial code developed under the supervision of Dr. Lesley Shannon,
+ * Reconfigurable Computing Lab, Simon Fraser University.
+ *
+ * Author(s):
+ *             Eric Matthews <ematthew@sfu.ca>
+ */
+
+import taiga_config::*;
+import taiga_types::*;
+
+module id_inuse (
+        input logic clk,
+        input logic rst,
+        input logic [4:0] rs1_addr,
+        input logic [4:0] rs2_addr,
+        input logic [4:0] issued_rd_addr,
+        input instruction_id_t issue_id,
+        input instruction_id_t retired_id,
+        input logic issued,
+        input logic retired,
+        output logic rs1_inuse,
+        output logic rs2_inuse
+        );
+    ////////////////////////////////////////////////////
+    logic [4:0] rd_addr_list [MAX_INFLIGHT_COUNT-1:0];
+
+    logic [MAX_INFLIGHT_COUNT-1:0] id_inuse;
+    logic [MAX_INFLIGHT_COUNT-1:0] id_inuse_new;
+
+    logic [MAX_INFLIGHT_COUNT-1:0] issue_id_one_hot;
+    logic [MAX_INFLIGHT_COUNT-1:0] retired_id_one_hot;
+    ////////////////////////////////////////////////////
+    //Implementation
+
+    always_comb begin
+        issue_id_one_hot = 0;
+        issue_id_one_hot[issue_id] = issued;
+
+        retired_id_one_hot = 0;
+        retired_id_one_hot[retired_id] = retired;
+
+        id_inuse_new = issue_id_one_hot | (id_inuse & ~retired_id_one_hot);
+    end
+
+    always_ff @ (posedge clk) begin
+        if (rst)
+            id_inuse <= '0;
+        else
+            id_inuse <= id_inuse_new;
+    end
+
+    always_ff @ (posedge clk) begin
+        if (issued)
+            rd_addr_list[issue_id] <= issued_rd_addr;
+    end
+
+    always_comb begin
+        rs1_inuse = 0;
+        rs2_inuse = 0;
+
+        foreach(rd_addr_list[i]) begin
+            rs1_inuse |= ({id_inuse[i], rd_addr_list[i]} == {1'b1, rs1_addr});
+            rs2_inuse |= ({id_inuse[i], rd_addr_list[i]} == {1'b1, rs2_addr});
+        end
+    end
+    ////////////////////////////////////////////////////
+    //End of Implementation
+    ////////////////////////////////////////////////////
+
+
+    ////////////////////////////////////////////////////
+    //Assertions
+
+endmodule
+
+
+
+

core/inuse.sv

@@ -1,109 +0,0 @@
-/*
- * Copyright © 2018-2019 Eric Matthews,  Lesley Shannon
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Initial code developed under the supervision of Dr. Lesley Shannon,
- * Reconfigurable Computing Lab, Simon Fraser University.
- *
- * Author(s):
- *             Eric Matthews <ematthew@sfu.ca>
- */
-
-import taiga_config::*;
-import taiga_types::*;
-
-module inuse (
-        input logic clk,
-        input logic rst,
-        input logic clr,
-        input logic [4:0] rs1_addr,
-        input logic [4:0] rs2_addr,
-        input logic [4:0] decode_rd_addr,
-        input logic [4:0] wb_rd_addr,
-        input logic issued,
-        input logic completed,
-        output logic rs1_inuse,
-        output logic rs2_inuse
-        );
-
-    //Memory organized as 2 sets of dual-ported memories
-    logic bankA [31:0];
-    logic bankB [31:0];
-
-    logic [4:0] w_clear;
-    logic [4:0] wb_rd_addr_muxed;
-    logic [4:0] decode_rd_addr_muxed;
-
-    logic wb_collision;
-    logic rd_inuse;
-    //////////////////////////////////////////
-    //Initialize to all inuse (0,1) for simulation,
-    //will be cleared by GC after reset in hardware
-    // synthesis translate_off
-    initial begin
-        foreach(bankA[i]) begin
-            bankA[i] = 0;
-            bankB[i] = 1;
-        end
-    end
-    // synthesis translate_on
-
-    //After reset, clear is held for at least 32 cycles to reset memory block
-    assign wb_rd_addr_muxed = clr ? w_clear : wb_rd_addr;
-    assign decode_rd_addr_muxed = clr ? w_clear : decode_rd_addr;
-
-    //reset is for simulation purposes only, not needed for actual design
-    always_ff @ (posedge clk) begin
-        if (rst)
-            w_clear <= 0;
-        else
-            w_clear <= w_clear + 5'(clr);
-    end
-
-    //Toggle issue (bankA) and write-back (bankB) values for inuse tracking
-    //Special cases are when multiple instructions are in flight that write to the same address
-    //Only the newest write will toggle BankB
-    //When issueing multiple times, don't toggle for subsequent issues unless the previous write is completing on this cycle
-	assign wb_collision = completed && (decode_rd_addr == wb_rd_addr);
-	assign rd_inuse = ~wb_collision & (bankA[decode_rd_addr_muxed] ^ bankB[decode_rd_addr_muxed]);
-
-    always_ff @ (posedge clk) begin
-        	bankA[decode_rd_addr_muxed] <= clr | ((~rd_inuse & issued) ^ bankA[decode_rd_addr_muxed]);
-    end
-
-    always_ff @ (posedge clk) begin
-        	bankB[wb_rd_addr_muxed] <= clr | (completed ^ bankB[wb_rd_addr_muxed]);
-    end
-
-    assign rs1_inuse = bankA[rs1_addr] ^ bankB[rs1_addr];
-    assign rs2_inuse = bankA[rs2_addr] ^ bankB[rs2_addr];
-
-    ////////////////////////////////////////////////////
-    //Assertions
-
-
-    ////////////////////////////////////////////////////
-    //Simulation Only
-    // synthesis translate_off
-    logic sim_inuse [31:0];
-    always_comb begin
-        foreach (sim_inuse[i])
-            sim_inuse[i] = bankA[i] ~^ bankB[i];
-    end
-    // synthesis translate_on
-
-endmodule
-
-
-

core/register_file.sv

@@ -63,12 +63,12 @@ module register_file(
             register[rf_wb.rd_addr] <= rf_wb.rd_data;
     end
 
-    inuse inuse_mem (.*,
-            .clr(inuse_clear),
-            .rs1_addr(rf_decode.rs1_addr),.rs2_addr(rf_decode.rs2_addr), .decode_rd_addr(rf_decode.future_rd_addr),
-            .wb_rd_addr(rf_wb.rd_addr),
+    id_inuse inuse_mem (.*,
+            .rs1_addr(rf_decode.rs1_addr),.rs2_addr(rf_decode.rs2_addr), .issued_rd_addr(rf_decode.future_rd_addr),
             .issued(rf_decode.instruction_issued),
-            .completed(valid_write & in_use_match),
+            .issue_id(rf_decode.id),
+            .retired_id(rf_wb.id),
+            .retired(valid_write),
             .rs1_inuse(rs1_inuse),
             .rs2_inuse(rs2_inuse)
             );
@@ -78,7 +78,6 @@ module register_file(
             in_use_by[rf_decode.future_rd_addr] <= rf_decode.id;
     end
 
-    assign in_use_match = (rf_wb.id == in_use_by[rf_wb.rd_addr]);
     assign rf_wb.rs1_id = in_use_by[rf_decode.rs1_addr];
     assign rf_wb.rs2_id = in_use_by[rf_decode.rs2_addr];
 

tools/taiga_compile_order

@@ -90,7 +90,7 @@
 ../core/pre_decode.sv
 ../core/decode.sv  
 
-../core/inuse.sv 
+../core/id_inuse.sv
 ../core/register_file.sv  
 
 ../core/id_tracking.sv