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Minor unused cleanups

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This commit is contained in:
Chris Keilbart 2024-09-09 13:28:03 -07:00
parent 309f58ab31
commit 528adc3986
7 changed files with 7 additions and 22 deletions
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4
core/common_components/cva5_fifo.sv
View file

@ -27,10 +27,6 @@
*/
module cva5_fifo
import cva5_config::*;
import riscv_types::*;
import cva5_types::*;
#(
parameter type DATA_TYPE = logic,
parameter FIFO_DEPTH = 4

8
core/common_components/lfsr.sv
View file

@ -68,7 +68,7 @@ module lfsr
logic feedback;
////////////////////////////////////////////////////
//Implementation
generate if (WIDTH == 2) begin : gen_width_two
generate if (WIDTH <= 2) begin : gen_width_one_or_two
assign feedback = ~value[WIDTH-1];
end
else begin : gen_width_three_plus
@ -84,8 +84,10 @@ module lfsr
always_ff @ (posedge clk) begin
if (NEEDS_RESET & rst)
value <= '0;
else if (en)
value <= {value[WIDTH-2:0], feedback};
else if (en) begin
value <= value << 1;
value[0] <= feedback;
end
end
endmodule

4
core/common_components/toggle_memory.sv
View file

@ -22,16 +22,12 @@
module toggle_memory
import cva5_config::*;
import cva5_types::*;
# (
parameter DEPTH = 8,
parameter NUM_READ_PORTS = 2
)
(
input logic clk,
input logic rst,
input logic toggle,
input logic [$clog2(DEPTH)-1:0] toggle_id,

8
core/common_components/toggle_memory_set.sv
View file

@ -22,9 +22,6 @@
module toggle_memory_set
import cva5_config::*;
import cva5_types::*;
# (
parameter DEPTH = 64,
parameter NUM_WRITE_PORTS = 3,
@ -32,7 +29,6 @@ module toggle_memory_set
)
(
input logic clk,
input logic rst,
input logic init_clear,
input logic toggle [NUM_WRITE_PORTS],
@ -53,7 +49,7 @@ module toggle_memory_set
//counter for indexing through memories for post-reset clearing/initialization
lfsr #(.WIDTH($clog2(DEPTH)), .NEEDS_RESET(0))
lfsr_counter (
.clk (clk), .rst (rst),
.clk (clk), .rst (1'b0),
.en(init_clear),
.value(clear_index)
);
@ -76,7 +72,7 @@ module toggle_memory_set
for (j = 0; j < NUM_WRITE_PORTS+1; j++) begin : write_port_gen
toggle_memory #(.DEPTH(DEPTH), .NUM_READ_PORTS(NUM_READ_PORTS+1))
mem (
.clk (clk), .rst (rst),
.clk (clk),
.toggle(_toggle[j]),
.toggle_id(_toggle_addr[j]),
.read_id(_read_addr),

1
core/instruction_metadata_and_id_management.sv
View file

@ -311,7 +311,6 @@ module instruction_metadata_and_id_management
) id_waiting_for_writeback_toggle_mem_set
(
.clk (clk),
.rst (rst),
.init_clear (gc.init_clear),
.toggle (id_waiting_toggle),
.toggle_addr (id_waiting_toggle_addr),

3
core/mmu/mmu.sv
View file

@ -22,9 +22,6 @@
module mmu
import cva5_config::*;
import riscv_types::*;
import cva5_types::*;
import csr_types::*;
(

1
core/register_file.sv
View file

@ -100,7 +100,6 @@ module register_file
) id_inuse_toggle_mem_set
(
.clk (clk),
.rst (rst),
.init_clear (gc.init_clear),
.toggle (toggle),
.toggle_addr (toggle_addr),