Removed unused signals, added additional linting criteria

core/alu_unit.sv

@@ -36,10 +36,8 @@ module alu_unit(
     logic[XLEN-1:0] rshift_result;
     logic[XLEN-1:0] lshift_result;
 
-    logic done;
     logic[XLEN:0] adder_in1;
     logic[XLEN:0] adder_in2;
-    logic[XLEN:0] adder_in2_logic;
 
     logic[XLEN-1:0] result;
     logic [31:0] rd_bank [MAX_INFLIGHT_COUNT-1:0];

core/barrel_shifter.sv

@@ -32,7 +32,7 @@ module barrel_shifter (
         output logic[XLEN-1:0] shifted_resultl
         );
 
-    logic[XLEN-1:0] shiftx8, shiftx2, shiftx1, shiftx1_l;
+    logic[XLEN-1:0] shiftx8, shiftx2, shiftx1;
     logic[XLEN-1:0] preshifted_input;
     //Bit flipping shared shifter
     always_comb begin

core/branch_unit.sv

@@ -48,21 +48,12 @@ module branch_unit(
     logic [31:0] jump_base;
     logic [31:0] jump_pc_dec;
 
-    logic signed [32:0] rs1_sext;
-    logic signed [32:0] rs2_sext;
-    logic signed [30:0] sub_toss;
-
     logic result;
     logic result_ex;
 
     logic [2:0] fn3_ex;
-    logic [31:0] rd_ex;
     logic jump_ex;
 
-    logic done;
-    logic new_jal_jalr_dec_with_rd;
-
-
     //Branch Predictor
     logic branch_taken;
     logic branch_correctly_taken;
@@ -80,8 +71,6 @@ module branch_unit(
     logic is_call;
     logic is_return;
 
-    logic [31:0] rd_bank [MAX_INFLIGHT_COUNT-1:0];
-    instruction_id_t id;
     //implementation
     ////////////////////////////////////////////////////
     assign issue.ready = 1;

core/csr_regs.sv

@@ -469,7 +469,7 @@ endgenerate
             minst_ret <= 0;
         end else begin
             mcycle <= mcycle + 1;
-            minst_ret <= minst_ret + inst_ret_inc;
+            minst_ret <= minst_ret + COUNTER_W'(inst_ret_inc);
         end
     end
 
@@ -498,8 +498,8 @@ endgenerate
             //Machine Timers and Counters
             MCYCLE : selected_csr = mcycle[XLEN-1:0];
             MINSTRET : selected_csr = minst_ret[XLEN-1:0];
-            MCYCLEH : selected_csr = mcycle[COUNTER_W-1:XLEN];
-            MINSTRETH : selected_csr = minst_ret[COUNTER_W-1:XLEN];
+            MCYCLEH : selected_csr = 32'(mcycle[COUNTER_W-1:XLEN]);
+            MINSTRETH : selected_csr = 32'(minst_ret[COUNTER_W-1:XLEN]);
 
            //Supervisor Trap Setup
            SSTATUS : selected_csr = (mstatus & mstatus_smask);
@@ -521,9 +521,9 @@ endgenerate
             CYCLE : selected_csr = mcycle[XLEN-1:0];
             TIME : selected_csr = mcycle[XLEN-1:0];
             INSTRET : selected_csr = minst_ret[XLEN-1:0];
-            CYCLEH : selected_csr = mcycle[COUNTER_W-1:XLEN];
-            TIMEH : selected_csr = mcycle[COUNTER_W-1:XLEN];
-            INSTRETH : selected_csr = minst_ret[COUNTER_W-1:XLEN];
+            CYCLEH : selected_csr = 32'(mcycle[COUNTER_W-1:XLEN]);
+            TIMEH : selected_csr = 32'(mcycle[COUNTER_W-1:XLEN]);
+            INSTRETH : selected_csr = 32'(minst_ret[COUNTER_W-1:XLEN]);
 
             default : begin selected_csr = 0; invalid_addr = 1; end
         endcase

core/decode.sv

@@ -95,15 +95,12 @@ module decode(
 
     logic [NUM_WB_UNITS-1:0] new_request_for_id_gen;
     logic [NUM_UNITS-1:0] new_request;
-    logic [WB_UNITS_WIDTH-1:0] new_request_int;
     logic [NUM_UNITS-1:0] issue_ready;
     logic [NUM_UNITS-1:0] issue;
 
     logic instruction_issued;
-
     logic valid_opcode;
 
-    instruction_id_t last_id;
     genvar i;
     ////////////////////////////////////////////////////
     //Implementation
@@ -404,7 +401,7 @@ module decode(
             assign unit_issue[i].instruction_id = ti.issue_id;
             assign unit_issue[i].instruction_id_one_hot = ti.issue_id_one_hot;
             always_ff @(posedge clk) begin
-                unit_issue[i].new_request_r = issue[i];
+                unit_issue[i].new_request_r <= issue[i];
             end
         end
     endgenerate

core/div_unit.sv

@@ -35,7 +35,6 @@ module div_unit
 
     logic computation_complete;
     logic div_done;
-    logic done;
 
     logic [31:0] quotient;
     logic [31:0] remainder;
@@ -56,7 +55,6 @@ module div_unit
     logic negateResult;
     logic divisor_zero;
 
-    logic [31:0] div_result_sign_corrected;
     logic [31:0] wb_div_result;
     logic [31:0] rd_bank [MAX_INFLIGHT_COUNT-1:0];
 
@@ -105,14 +103,14 @@ module div_unit
 
     ////////////////////////////////////////////////////
     //Input Processing
-    assign complementerA = ({32{dividend_signed}} ^ stage1.rs1) + dividend_signed;
-    assign complementerB = ({32{divisor_signed}} ^ stage1.rs2) + divisor_signed;
+    assign complementerA = ({32{dividend_signed}} ^ stage1.rs1) + 32'(dividend_signed);
+    assign complementerB = ({32{divisor_signed}} ^ stage1.rs2) + 32'(divisor_signed);
 
     ////////////////////////////////////////////////////
     //Output muxing
     assign negateResult = stage1.op[1] ? remainder_signed : (~divisor_zero & quotient_signed);
     assign result_input = stage1.op[1] ? remainder : quotient;
-    assign wb_div_result = ({32{negateResult}} ^ result_input) + negateResult;
+    assign wb_div_result = ({32{negateResult}} ^ result_input) + 32'(negateResult);
 
     ////////////////////////////////////////////////////
     //Div core

core/id_stack.sv

@@ -59,7 +59,7 @@ module id_stack # (
     //Initial ordering, stack has no reset, as ID ordering is arbitrary
     initial begin
         for (int i=0; i<STACK_DEPTH; i++) begin
-            stack[i] = i;
+            stack[i] = i[STACK_DEPTH_W-1:0];
         end
     end
 
@@ -103,7 +103,7 @@ module id_stack # (
         if (rst)
             next_id_index <= '1;
         else
-            next_id_index <= next_id_index + retired + store_committed - issued;
+            next_id_index <= next_id_index + STACK_DEPTH_W'(retired) + STACK_DEPTH_W'(store_committed) - STACK_DEPTH_W'(issued);
     end
 
     assign next_id = stack[next_id_index[STACK_DEPTH_W-1:0]];

core/interfaces.sv

@@ -37,14 +37,13 @@ interface branch_predictor_interface;
     logic [BRANCH_PREDICTOR_WAYS-1:0] update_way;
     logic use_ras;
     branch_predictor_metadata_t metadata;
-    logic flush;
 
     modport branch_predictor (
         input if_pc, new_mem_request, next_pc,
-        output branch_flush_pc, predicted_pc, use_prediction, update_way, use_ras, metadata, flush
+        output branch_flush_pc, predicted_pc, use_prediction, update_way, use_ras, metadata
     );
     modport fetch (
-        input branch_flush_pc, predicted_pc, use_prediction, update_way, use_ras, metadata, flush,
+        input branch_flush_pc, predicted_pc, use_prediction, update_way, use_ras, metadata,
         output if_pc, new_mem_request, next_pc
      );
 
@@ -192,7 +191,7 @@ interface mmu_interface;
     logic [21:0] ppn;
     logic mxr; //Make eXecutable Readable
     logic pum; //Protect User Memory
-    logic privilege;
+    logic [1:0] privilege;
 
     modport mmu (input virtual_address, new_request, execute, rnw, ppn, mxr, pum, privilege, output write_entry, new_phys_addr);
     modport tlb (input write_entry, new_phys_addr, output new_request, virtual_address, execute, rnw);

core/load_store_unit.sv

@@ -87,8 +87,6 @@ module load_store_unit (
     logic [31:0] aligned_load_data;
     logic [31:0] final_load_data;
 
-    logic [31:0] forwarded_data;
-
     logic [31:0] rd_bank [MAX_INFLIGHT_COUNT-1:0];
     logic [31:0] previous_load;
     logic [31:0] stage1_raw_data;

core/ras.sv

@@ -31,8 +31,9 @@ module ras (
 
     logic[31:0] lut_ram [RAS_DEPTH-1:0];
 
-    logic[$clog2(RAS_DEPTH)-1:0] read_index;
-    logic[$clog2(RAS_DEPTH)-1:0] write_index;
+    localparam RAS_DEPTH_W = $clog2(RAS_DEPTH);
+    logic[RAS_DEPTH_W-1:0] read_index;
+    logic[RAS_DEPTH_W-1:0] write_index;
     logic valid_chain[RAS_DEPTH-1:0];
     logic valid_chain_update;
     ///////////////////////////////////////////////////////
@@ -61,7 +62,7 @@ module ras (
         else if (ras.pop & ~ras.push)
             read_index <= read_index - 1;
     end
-    assign write_index = (ras.push & ~ras.pop) ? (read_index + valid_chain[read_index]) : read_index;
+    assign write_index = (ras.push & ~ras.pop) ? (read_index + RAS_DEPTH_W'(valid_chain[read_index])) : read_index;
     
     assign valid_chain_update = ras.push | ras.pop;
     always_ff @ (posedge clk) begin

core/taiga.sv

@@ -77,7 +77,6 @@ module taiga (
     tlb_interface dtlb();
     logic tlb_on;
     logic [ASIDLEN-1:0] asid;
-    logic return_from_exception;
 
     //Pre-Decode
     logic pre_decode_push;
@@ -97,11 +96,9 @@ module taiga (
     logic gc_fetch_flush;
     logic gc_fetch_pc_override;
     logic gc_supress_writeback;
-    logic gc_flush_LS_input;
     logic inorder;
     logic inuse_clear;
     instruction_id_t oldest_id;
-    logic inflight_queue_empty;
     logic load_store_issue;
     logic [31:0] gc_fetch_pc;
 
@@ -113,21 +110,13 @@ module taiga (
     instruction_id_one_hot_t csr_id_done;
     logic csr_done;
 
-    //Branch Unit and Fetch Unit
-    logic branch_taken;
-    logic [31:0] pc_offset;
-    logic[31:0] jalr_rs1;
-    logic jalr;
-
     //Decode Unit and Fetch Unit
     logic illegal_instruction;
-
     logic instruction_queue_empty;
 
     logic instruction_issued_no_rd;
     logic instruction_issued_with_rd;
     logic instruction_complete;
-    logic instruction_issued;
     logic gc_flush_required;
     logic branch_issued;
 

core/taiga_fifo.sv

@@ -42,7 +42,6 @@ module taiga_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, paramet
     localparam LOG2_FIFO_DEPTH = $clog2(FIFO_DEPTH);
     logic[LOG2_FIFO_DEPTH-1:0] write_index;
     logic[LOG2_FIFO_DEPTH-1:0] read_index;
-    logic two_plus;
 
     genvar i;
 
@@ -118,19 +117,19 @@ module taiga_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, paramet
                     srl_index[SRL_DEPTH_W-1] <= 0;
                     srl_index[SRL_DEPTH_W-2:0] <= '1;
                 end else
-                    srl_index <= srl_index + fifo.push - fifo.pop;
+                    srl_index <= srl_index + SRL_DEPTH_W'(fifo.push) - SRL_DEPTH_W'(fifo.pop);
             end
 
             //Helper expressions
-            assign full = fifo.valid && (srl_index[SRL_DEPTH_W-2:0] == (FIFO_DEPTH-1));
-            assign full_minus_one = fifo.valid && (srl_index[SRL_DEPTH_W-2:0] == (FIFO_DEPTH-2));
+            assign full = fifo.valid && (srl_index[SRL_DEPTH_W-2:0] == (SRL_DEPTH_W-1)'(FIFO_DEPTH-1));
+            assign full_minus_one = fifo.valid && (srl_index[SRL_DEPTH_W-2:0] == (SRL_DEPTH_W-1)'(FIFO_DEPTH-2));
             assign one_entry = fifo.valid && (srl_index[SRL_DEPTH_W-2:0] == 0);
 
             assign fifo.valid = srl_index[SRL_DEPTH_W-1];
             assign fifo.empty = ~fifo.valid;
 
             always_ff @ (posedge clk) begin
-                fifo.full = ~fifo.pop & ((fifo.push & full_minus_one) | full);
+                fifo.full <= ~fifo.pop & ((fifo.push & full_minus_one) | full);
             end
 
             assign fifo.almost_empty = one_entry;

core/write_back.sv

@@ -66,7 +66,6 @@ module write_back(
     logic [MAX_INFLIGHT_COUNT-1:0] id_done_ordered_post_store;
 
     logic retired, retired_r;
-    logic first_cycle_completion_abort;
     ////////////////////////////////////////////////////
     //Implementation
 
@@ -135,9 +134,9 @@ module write_back(
 
     always_ff @ (posedge clk) begin
         if (rst)
-            id_done_r = '0;
+            id_done_r <= '0;
         else
-            id_done_r = id_done;
+            id_done_r <= id_done;
     end
 
     assign retired = (inorder ? id_done_ordered[MAX_INFLIGHT_COUNT-1] : |id_done);

tools/Makefile

@@ -98,6 +98,13 @@ lint:
 	../test_benches/verilator/taiga_local_mem.sv \
 	--top-module taiga_local_mem \
 	--lint-only
+
+.PHONY: lint_full
+lint_full:
+	verilator -cc $(TAIGA_SRCS) \
+	../test_benches/verilator/taiga_local_mem.sv \
+	--top-module taiga_local_mem \
+	--lint-only -Wwarn-lint -Wwarn-style
 		
 .PHONY: verilator_taiga_dhrystone
 verilator_taiga_dhrystone: