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code cleanups

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This commit is contained in:
Eric Matthews 2019-09-03 10:44:39 -07:00
parent db775b826e
commit 863c7ae6e6
6 changed files with 42 additions and 54 deletions
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16
core/branch_unit.sv
View file

@ -38,7 +38,7 @@ module branch_unit(
output logic tr_return_misspredict
);
logic branch_issued;
logic branch_issued_r;
logic[19:0] jal_imm;
logic[11:0] jalr_imm;
@ -78,11 +78,11 @@ module branch_unit(
//Branch new request is held if the following instruction hasn't arrived at decode/issue yet
always_ff @(posedge clk) begin
if (rst)
branch_issued <= 0;
branch_issued_r <= 0;
else if (issue.new_request)
branch_issued <= 1;
branch_issued_r <= 1;
else if (branch_inputs.dec_pc_valid )
branch_issued <= 0;
branch_issued_r <= 0;
end
branch_comparator bc (
@ -93,7 +93,7 @@ module branch_unit(
.result(result)
);
assign branch_taken = branch_issued & ((~jump_ex & (result_ex ^ fn3_ex[0])) | jump_ex);
assign branch_taken = branch_issued_r & ((~jump_ex & (result_ex ^ fn3_ex[0])) | jump_ex);
assign jal_imm = {branch_inputs.instruction[31], branch_inputs.instruction[19:12], branch_inputs.instruction[20], branch_inputs.instruction[30:21]};
@ -145,7 +145,7 @@ module branch_unit(
assign br_results.branch_ex_metadata = branch_metadata;
assign br_results.branch_taken = branch_taken;
assign br_results.branch_ex = branch_issued & branch_inputs.dec_pc_valid;
assign br_results.branch_ex = branch_issued_r & branch_inputs.dec_pc_valid;
assign br_results.is_return_ex = is_return;
assign br_results.branch_prediction_used = branch_prediction_used;
assign br_results.bp_update_way = bp_update_way;
@ -153,9 +153,9 @@ module branch_unit(
assign branch_correctly_taken = {br_results.branch_taken, branch_inputs.dec_pc[31:1]} == {1'b1, br_results.jump_pc[31:1]};
assign branch_correclty_not_taken = {br_results.branch_taken, branch_inputs.dec_pc[31:1]} == {1'b0, br_results.njump_pc[31:1]};
assign miss_predict = branch_issued && branch_inputs.dec_pc_valid && ~(branch_correctly_taken || branch_correclty_not_taken);
assign miss_predict = branch_issued_r && branch_inputs.dec_pc_valid && ~(branch_correctly_taken || branch_correclty_not_taken);
assign branch_flush = USE_BRANCH_PREDICTOR ? miss_predict : branch_issued & branch_taken & branch_inputs.dec_pc_valid;
assign branch_flush = USE_BRANCH_PREDICTOR ? miss_predict : branch_issued_r & branch_taken & branch_inputs.dec_pc_valid;
//RAS support
////////////////////////////////////////////////////

39
core/decode.sv
View file

@ -78,7 +78,6 @@ module decode(
logic [4:0] rs1_addr;
logic [4:0] rs2_addr;
logic [4:0] future_rd_addr;
unit_id_t unit_id;
logic nop;
@ -101,6 +100,15 @@ module decode(
logic instruction_issued;
logic valid_opcode;
//LS-inputs
logic [11:0] ls_offset;
logic is_load;
logic is_store;
logic amo_op;
logic store_conditional;
logic load_reserve;
logic [4:0] amo_type;
genvar i;
////////////////////////////////////////////////////
//Implementation
@ -126,16 +134,14 @@ module decode(
////////////////////////////////////////////////////
//Register File interface inputs
assign rf_decode.rs1_addr = rs1_addr;
assign rf_decode.rs2_addr = rs2_addr;
assign rf_decode.future_rd_addr = future_rd_addr;
assign rf_decode.rs1_addr = rs1_addr;
assign rf_decode.rs2_addr = rs2_addr;
assign rf_decode.future_rd_addr = future_rd_addr;
assign rf_decode.instruction_issued = instruction_issued_with_rd & ~rd_zero;
assign rf_decode.id = ti.issue_id;
assign rf_decode.unit_id = unit_id;
assign rf_decode.uses_rs1 = uses_rs1;
assign rf_decode.uses_rs2 = uses_rs2;
////////////////////////////////////////////////////
//Tracking Interface
always_comb begin
@ -143,11 +149,9 @@ module decode(
new_request_for_id_gen[LS_UNIT_WB_ID] |= new_request[GC_UNIT_ID];
end
one_hot_to_integer #(NUM_WB_UNITS) new_request_to_int (.*, .one_hot(new_request_for_id_gen), .int_out(unit_id));
assign ti.inflight_packet.rd_addr = future_rd_addr;
assign ti.inflight_packet.rd_addr_nzero = ~rd_zero;
assign ti.inflight_packet.is_store = (opcode_trim == STORE_T) || (amo_op && store_conditional);
assign ti.inflight_packet.is_store = is_store;
assign ti.issued = instruction_issued & (uses_rd | new_request[LS_UNIT_WB_ID]);
////////////////////////////////////////////////////
@ -182,7 +186,7 @@ module decode(
assign issue_valid = fb_valid & ti.id_available & ~gc_issue_hold & ~gc_fetch_flush;
assign operands_ready = ~rf_decode.rs1_conflict & ~rf_decode.rs2_conflict;
assign load_store_operands_ready = ~rf_decode.rs1_conflict & (~rf_decode.rs2_conflict | (rf_decode.rs2_conflict & load_store_forward_possible));
assign load_store_operands_ready = ~rf_decode.rs1_conflict & (~rf_decode.rs2_conflict | (rf_decode.rs2_conflict & load_store_forward_possible));
//All units share the same operand ready logic except load-store which has an internal forwarding path
always_comb begin
@ -235,14 +239,6 @@ module decode(
////////////////////////////////////////////////////
//Load Store unit inputs
logic [11:0] ls_offset;
logic ls_is_load;
logic amo_op;
logic store_conditional;
logic load_reserve;
logic [4:0] amo_type;
assign amo_op = USE_AMO ? (opcode_trim == AMO_T) : 1'b0;
assign amo_type = fb.instruction[31:27];
assign store_conditional = (amo_type == AMO_SC);
@ -259,7 +255,8 @@ module decode(
end
endgenerate
assign ls_is_load = (opcode_trim inside {LOAD_T, AMO_T}) && !(amo_op & store_conditional); //LR and AMO_ops perform a read operation as well
assign is_load = (opcode_trim inside {LOAD_T, AMO_T}) && !(amo_op & store_conditional); //LR and AMO_ops perform a read operation as well
assign is_store = (opcode_trim == STORE_T) || (amo_op && store_conditional);//Used for LS unit and for ID tracking
assign ls_offset = opcode[5] ? {fb.instruction[31:25], fb.instruction[11:7]} : fb.instruction[31:20];
assign ls_inputs.offset = ls_offset;
@ -267,8 +264,8 @@ module decode(
assign ls_inputs.rs2 = rf_decode.rs2_data;
assign ls_inputs.pc = fb.pc;
assign ls_inputs.fn3 = amo_op ? LS_W_fn3 : fn3;
assign ls_inputs.load = ls_is_load;
assign ls_inputs.store = (opcode_trim == STORE_T) || (amo_op && store_conditional);
assign ls_inputs.load = is_load;
assign ls_inputs.store = is_store;
assign ls_inputs.load_store_forward = rf_decode.rs2_conflict;
assign ls_inputs.instruction_id = ti.issue_id;

5
core/interfaces.sv
View file

@ -107,7 +107,6 @@ interface register_file_decode_interface;
logic[4:0] rs2_addr; //if not used required to be zero
logic[XLEN-1:0] rs2_data;
instruction_id_t id;
unit_id_t unit_id;
logic uses_rs1;
logic uses_rs2;
@ -115,8 +114,8 @@ interface register_file_decode_interface;
logic rs2_conflict;
logic instruction_issued;
modport decode (output future_rd_addr, rs1_addr, rs2_addr, instruction_issued, id, unit_id, uses_rs1, uses_rs2, input rs1_conflict, rs2_conflict, rs1_data, rs2_data);
modport unit (input future_rd_addr, rs1_addr, rs2_addr, instruction_issued, id, unit_id, uses_rs1, uses_rs2, output rs1_conflict, rs2_conflict, rs1_data, rs2_data);
modport decode (output future_rd_addr, rs1_addr, rs2_addr, instruction_issued, id, uses_rs1, uses_rs2, input rs1_conflict, rs2_conflict, rs1_data, rs2_data);
modport unit (input future_rd_addr, rs1_addr, rs2_addr, instruction_issued, id, uses_rs1, uses_rs2, output rs1_conflict, rs2_conflict, rs1_data, rs2_data);
endinterface

2
core/load_store_unit.sv
View file

@ -72,6 +72,7 @@ module load_store_unit (
ls_sub_unit_interface #(.BASE_ADDR(MEMORY_ADDR_L), .UPPER_BOUND(MEMORY_ADDR_H), .BIT_CHECK(BUS_BIT_CHECK)) cache();
logic units_ready;
logic store_bypass_stall;
logic issue_request;
logic load_complete;
logic store_complete;
@ -142,7 +143,6 @@ module load_store_unit (
//When switching units, ensure no outstanding loads so that there can be no timing collisions with results
assign unit_stall = (current_unit != last_unit) && ~load_attributes.empty;
logic store_bypass_stall;
assign store_bypass_stall = stage1.store & stage1.load_store_forward & ~load_attributes.empty;
assign issue_request = input_fifo.valid & units_ready & ~unit_stall & ~unaligned_addr & ~store_bypass_stall;

4
core/register_file.sv
View file

@ -51,10 +51,8 @@ module register_file(
//////////////////////////////////////////
//Assign zero to r0 and initialize all registers to zero
initial begin
for (int i=0; i<32; i++) begin
for (int i=0; i<32; i++)
register[i] = 0;
in_use_by[i] = '0;
end
end
//Writeback unit does not assert rf_wb.commit when the target register is r0

30
core/write_back.sv
View file

@ -88,17 +88,15 @@ module write_back(
end
end
always_comb begin
foreach(rds_by_id_next[i]) begin
rds_by_id_next[i] = unit_rd[id_unit_select[i]];
generate
for (i=0; i< MAX_INFLIGHT_COUNT; i++) begin
assign rds_by_id_next[i] = unit_rd[id_unit_select[i]];
always_ff @ (posedge clk) begin
if (id_done_new[i])
rds_by_id[i] <= rds_by_id_next[i];
end
end
end
always_ff @ (posedge clk) begin
foreach(rds_by_id_next[i]) begin
if (id_done_new[i])
rds_by_id[i] <= rds_by_id_next[i];
end
end
endgenerate
//ID tracking
id_tracking id_fifos (.*, .issued(ti.issued), .retired(retired), .id_available(ti.id_available),
@ -108,16 +106,14 @@ module write_back(
//Inflight Instruction ID table
//Stores rd_addr and whether rd_addr is zero
initial begin
foreach (packet_table[i]) begin
packet_table[i] = '0;
end
end
always_ff @ (posedge clk) begin
if (ti.id_available)//instruction_issued_with_rd
packet_table[issue_id] <= ti.inflight_packet;
end
always_ff @ (posedge clk) begin
retired_instruction_packet <= instruction_queue_empty ? ti.inflight_packet : packet_table[retired_id];
end
//////////////////////
//One-hot ID retired last cycle
@ -149,8 +145,6 @@ module write_back(
retired_id_r <= retired_id;
end
//Read table for unit ID (acks, and rd_addr for register file)
assign retired_instruction_packet = packet_table[retired_id_r];
assign instruction_complete = retired_r & ~retired_instruction_packet.is_store;
//Register file interaction