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created new fault-tolerant Taiga branch

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stuartjh 2020-08-12 10:34:19 -07:00 • committed by Eric Matthews
parent 01700d108e
commit cd80e73dd6
1 changed files with 84 additions and 0 deletions
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formal/scripts/taiga_rtl.vfile Normal file
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+incdir+${JG_TAIGA_RTL_PATH} \
${JG_TAIGA_RTL_PATH}/core/taiga_config.sv \
${JG_TAIGA_RTL_PATH}/core/riscv_types.sv \
${JG_TAIGA_RTL_PATH}/core/taiga_types.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_config_and_types.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_interfaces.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_external_interfaces.sv \
${JG_TAIGA_RTL_PATH}/local_memory/local_memory_interface.sv \
${JG_TAIGA_RTL_PATH}/local_memory/local_mem.sv \
${JG_TAIGA_RTL_PATH}/core/interfaces.sv \
${JG_TAIGA_RTL_PATH}/core/external_interfaces.sv \
${JG_TAIGA_RTL_PATH}/core/csr_types.sv \
${JG_TAIGA_RTL_PATH}/core/csr_regs.sv \
${JG_TAIGA_RTL_PATH}/core/gc_unit.sv \
${JG_TAIGA_RTL_PATH}/core/branch_comparator.sv \
${JG_TAIGA_RTL_PATH}/core/branch_unit.sv \
${JG_TAIGA_RTL_PATH}/core/barrel_shifter.sv \
${JG_TAIGA_RTL_PATH}/core/alu_unit.sv \
${JG_TAIGA_RTL_PATH}/core/axi_master.sv \
${JG_TAIGA_RTL_PATH}/core/avalon_master.sv \
${JG_TAIGA_RTL_PATH}/core/wishbone_master.sv \
${JG_TAIGA_RTL_PATH}/core/axi_to_arb.sv \
${JG_TAIGA_RTL_PATH}/core/one_hot_occupancy.sv \
${JG_TAIGA_RTL_PATH}/core/binary_occupancy.sv \
${JG_TAIGA_RTL_PATH}/core/taiga_fifo.sv \
${JG_TAIGA_RTL_PATH}/core/shift_counter.sv \
${JG_TAIGA_RTL_PATH}/core/set_clr_reg_with_rst.sv \
${JG_TAIGA_RTL_PATH}/core/intel/intel_byte_enable_ram.sv \
${JG_TAIGA_RTL_PATH}/core/xilinx/xilinx_byte_enable_ram.sv \
${JG_TAIGA_RTL_PATH}/core/byte_en_BRAM.sv \
${JG_TAIGA_RTL_PATH}/core/one_hot_to_integer.sv \
${JG_TAIGA_RTL_PATH}/core/cycler.sv \
${JG_TAIGA_RTL_PATH}/core/tag_bank.sv \
${JG_TAIGA_RTL_PATH}/core/dbram.sv \
${JG_TAIGA_RTL_PATH}/core/ddata_bank.sv \
${JG_TAIGA_RTL_PATH}/core/dtag_banks.sv \
${JG_TAIGA_RTL_PATH}/core/amo_alu.sv \
${JG_TAIGA_RTL_PATH}/core/dcache.sv \
${JG_TAIGA_RTL_PATH}/core/load_store_queue.sv \
${JG_TAIGA_RTL_PATH}/core/load_store_unit.sv \
${JG_TAIGA_RTL_PATH}/core/ibram.sv \
${JG_TAIGA_RTL_PATH}/core/itag_banks.sv \
${JG_TAIGA_RTL_PATH}/core/icache.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_radix2.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_radix2_ET.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_radix2_ET_full.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_radix4.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_radix8.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_radix8_ET.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_radix4_ET.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_radix4_ET_full.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_radix16.sv \
${JG_TAIGA_RTL_PATH}/core/msb.sv \
${JG_TAIGA_RTL_PATH}/core/msb_naive.sv \
${JG_TAIGA_RTL_PATH}/core/clz.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_quick_clz_mk2.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_quick_clz.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_quick_radix4.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_quick_naive.sv \
${JG_TAIGA_RTL_PATH}/core/div_algorithms/div_algorithm.sv \
${JG_TAIGA_RTL_PATH}/core/div_unit.sv \
${JG_TAIGA_RTL_PATH}/core/lut_ram.sv \
${JG_TAIGA_RTL_PATH}/core/tlb_lut_ram.sv \
${JG_TAIGA_RTL_PATH}/core/mmu.sv \
${JG_TAIGA_RTL_PATH}/core/mul_unit.sv \
${JG_TAIGA_RTL_PATH}/core/l1_arbiter.sv \
${JG_TAIGA_RTL_PATH}/core/ras.sv \
${JG_TAIGA_RTL_PATH}/core/branch_predictor_ram.sv \
${JG_TAIGA_RTL_PATH}/core/branch_predictor.sv \
${JG_TAIGA_RTL_PATH}/core/fetch.sv \
${JG_TAIGA_RTL_PATH}/core/pre_decode.sv \
${JG_TAIGA_RTL_PATH}/core/illegal_instruction_checker.sv \
${JG_TAIGA_RTL_PATH}/core/decode_and_issue.sv \
${JG_TAIGA_RTL_PATH}/core/id_inuse.sv \
${JG_TAIGA_RTL_PATH}/core/reg_inuse.sv \
${JG_TAIGA_RTL_PATH}/core/register_file.sv \
${JG_TAIGA_RTL_PATH}/core/id_tracking.sv \
${JG_TAIGA_RTL_PATH}/core/write_back.sv \
${JG_TAIGA_RTL_PATH}/core/placer_randomizer.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_fifo.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_reservation_logic.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_round_robin.sv \
${JG_TAIGA_RTL_PATH}/l2_arbiter/l2_arbiter.sv \
${JG_TAIGA_RTL_PATH}/core/taiga.sv \