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writeback one-hot to mux

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This commit is contained in:
Eric Matthews 2019-08-20 22:08:17 -07:00
parent 1a548616b4
commit d368f2f4d5
4 changed files with 9 additions and 16 deletions
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5
core/decode.sv
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@ -140,12 +140,11 @@ module decode(
////////////////////////////////////////////////////
//Tracking Interface
assign ti.inflight_packet.unit_id = new_request;
//assign ti.inflight_packet.unit_id = new_request;
assign ti.inflight_packet.rd_addr = future_rd_addr;
assign ti.inflight_packet.rd_addr_nzero = ~rd_zero;
assign ti.issued = instruction_issued & (uses_rd | new_request[LS_UNIT_WB_ID]);
one_hot_to_integer #(NUM_WB_UNITS) new_request_to_int (.*, .one_hot(new_request), .int_out(ti.inflight_packet.unit_id));
////////////////////////////////////////////////////
//Unit Determination
assign mult_div_op = ib.data_out.instruction[25];

2
core/taiga_config.sv
View file

@ -189,7 +189,7 @@ package taiga_config;
parameter ALU_UNIT_WB_ID = 0;
parameter GC_UNIT_WB_ID = 1;//uses accepted
parameter GC_UNIT_WB_ID = 1;
parameter BRANCH_UNIT_WB_ID = 2;
parameter LS_UNIT_WB_ID = 3;
parameter DIV_UNIT_WB_ID = LS_UNIT_WB_ID + USE_DIV;

2
core/taiga_types.sv
View file

@ -256,7 +256,7 @@ package taiga_types;
} exception_packet_t;
typedef struct packed{
logic [NUM_WB_UNITS-1:0] unit_id;
logic [$clog2(NUM_WB_UNITS)-1:0] unit_id;
logic [4:0] rd_addr;
logic rd_addr_nzero;
} inflight_instruction_packet;

16
core/write_back.sv
View file

@ -50,8 +50,7 @@ module write_back(
//aliases for write-back-interface signals
logic [MAX_INFLIGHT_COUNT-1:0] unit_done_next_cycle [NUM_WB_UNITS-1:0];
logic [XLEN-1:0] unit_rd [NUM_WB_UNITS-1:0];
logic [NUM_WB_UNITS-1:0] accepted;
logic [XLEN-1:0] unit_rd [2**($clog2(NUM_WB_UNITS))-1:0];
/////
instruction_id_t issue_id, retired_id, retired_id_r;
@ -76,9 +75,10 @@ module write_back(
for (i=0; i< NUM_WB_UNITS; i++) begin : interface_to_array_g
assign unit_done_next_cycle[i] = unit_wb[i].done_next_cycle;
assign unit_rd[i] = unit_wb[i].rd;
assign unit_wb[i].accepted = accepted[i];
assign unit_wb[i].writeback_instruction_id = retired_id_r;
end
assign unit_rd[6] = unit_rd[GC_UNIT_WB_ID];
assign unit_rd[7] = unit_rd[ALU_UNIT_WB_ID];
endgenerate
//ID stack. id_ordering[0] is the next ID to be issued. Entries filled from
@ -170,8 +170,6 @@ module write_back(
//Read table for unit ID (acks, and rd_addr for register file)
assign retired_instruction_packet = packet_table[retired_id_r];
//assign accepted = retired_instruction_packet.unit_id & {NUM_WB_UNITS{retired_r}};
assign instruction_complete = retired_r;
//Register file interaction
@ -180,12 +178,8 @@ module write_back(
assign rf_wb.valid_write = retired_r;
assign rf_wb.rd_nzero = retired_instruction_packet.rd_addr_nzero;
always_comb begin
rf_wb.rd_data = 0;
for (int i=0; i< NUM_WB_UNITS; i++) begin
rf_wb.rd_data |= unit_rd[i] & {32{retired_instruction_packet.unit_id[i]}};
end
end
assign rf_wb.rd_data = unit_rd[retired_instruction_packet.unit_id];
////////////////////////////////////////////////////
//End of Implementation