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prep for CSR split

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This commit is contained in:
Eric Matthews 2021-10-28 10:55:51 -07:00
parent 7e0f920a12
commit d3c5471907
3 changed files with 2 additions and 10 deletions
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0
core/csr_regs.sv → core/csr_unit.sv
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10
core/gc_unit.sv
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@ -133,7 +133,6 @@ module gc_unit
typedef enum {RST_STATE, PRE_CLEAR_STATE, INIT_CLEAR_STATE, IDLE_STATE, TLB_CLEAR_STATE, IQ_DRAIN} gc_state;
gc_state state;
gc_state next_state;
gc_state prev_state;
logic init_clear_done;
logic tlb_clear_done;
@ -206,13 +205,6 @@ module gc_unit
state <= next_state;
end
always @(posedge clk) begin
if (rst)
prev_state <= RST_STATE;
else
prev_state <= state;
end
always_comb begin
next_state = state;
case (state)
@ -308,7 +300,7 @@ module gc_unit
////////////////////////////////////////////////////
//CSR registers
csr_regs # (.CONFIG(CONFIG))
csr_unit # (.CONFIG(CONFIG))
csr_registers (
.clk(clk), .rst(rst),
.csr_inputs(csr_inputs),

2
tools/taiga_compile_order
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@ -11,7 +11,7 @@ local_memory/local_mem.sv
core/interfaces.sv
core/external_interfaces.sv
core/csr_regs.sv
core/csr_unit.sv
core/gc_unit.sv
core/branch_comparator.sv