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Eric Matthews 2019-08-19 14:51:02 -07:00
parent 976ad3d5ee
commit e41fb648be
2 changed files with 24 additions and 25 deletions
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10
core/load_store_unit.sv
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@ -221,19 +221,17 @@ module load_store_unit (
assign shared_inputs.fn3 = stage1.fn3;
logic forward_data;
assign forward_data = stage1.load_store_forward | dcache_forward_data;
assign forward_data = stage1.load_store_forward;
assign stage1_raw_data = forward_data ? previous_load : stage1.rs2;
//Input: ABCD
//Assuming aligned requests,
//Possible byte selections: (A/C/D, B/D, C/D, D)
logic [1:0] data_in_mux;
always_comb begin
data_in_mux = dcache_forward_data ? dcache_stage2_fn3[1:0] : virtual_address[1:0];
shared_inputs.data_in[7:0] = stage1_raw_data[7:0];
shared_inputs.data_in[15:8] = (data_in_mux == 2'b01) ? stage1_raw_data[7:0] : stage1_raw_data[15:8];
shared_inputs.data_in[23:16] = (data_in_mux == 2'b10) ? stage1_raw_data[7:0] : stage1_raw_data[23:16];
case(data_in_mux)
shared_inputs.data_in[15:8] = (virtual_address[1:0] == 2'b01) ? stage1_raw_data[7:0] : stage1_raw_data[15:8];
shared_inputs.data_in[23:16] = (virtual_address[1:0] == 2'b10) ? stage1_raw_data[7:0] : stage1_raw_data[23:16];
case(virtual_address[1:0])
2'b10 : shared_inputs.data_in[31:24] = stage1_raw_data[15:8];
2'b11 : shared_inputs.data_in[31:24] = stage1_raw_data[7:0];
default : shared_inputs.data_in[31:24] = stage1_raw_data[31:24];

39
core/xilinx_byte_enable_ram.sv
View file

@ -52,32 +52,33 @@ module xilinx_byte_enable_ram #(
$readmemh(preload_file,ram, 0, LINES-1);
end
always_ff @(posedge clk) begin
if (en_a) begin
for (int i=0; i < 4; i++) begin
if (be_a[i])
generate
genvar i;
for (i=0; i < 4; i++) begin
always_ff @(posedge clk) begin
if (en_a) begin
if (be_a[i]) begin
ram[addr_a][8*i+:8] <= data_in_a[8*i+:8];
data_out_a[8*i+:8] <= data_in_a[8*i+:8];
end else begin
data_out_a[8*i+:8] <= ram[addr_a][8*i+:8];
end
end
end
end
always_ff @(posedge clk) begin
if (en_a)
data_out_a <= ram[addr_a];
end
always_ff @(posedge clk) begin
if (en_b) begin
for (int i=0; i < 4; i++) begin
if (be_b[i])
for (i=0; i < 4; i++) begin
always_ff @(posedge clk) begin
if (en_b) begin
if (be_b[i]) begin
ram[addr_b][8*i+:8] <= data_in_b[8*i+:8];
data_out_b[8*i+:8] <= data_in_b[8*i+:8];
end else begin
data_out_b[8*i+:8] <= ram[addr_b][8*i+:8];
end
end
end
end
always_ff @(posedge clk) begin
if (en_b)
data_out_b <= ram[addr_b];
end
endgenerate
endmodule