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Merge branch 'os-fixes6' of github.com:CKeilbar/ck-cva5 into os-fixes6

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msa417 2025-01-31 11:14:03 -08:00
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1
.gitignore vendored
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@ -1 +1,2 @@
test_benches/verilator/build
vivado/

4
README.md
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@ -7,8 +7,6 @@ The CVA5 is derived from the Taiga Project from Simon Fraser University.
The pipeline has been designed to support parallel, variable-latency execution units and to readily support the inclusion of new execution units.
![CVA5 Block Diagram](examples/zedboard/cva5_small.png)
## Documentation and Project Setup
For up-to-date documentation, as well as an automated build environment setup, refer to [Taiga Project](https://gitlab.com/sfu-rcl/taiga-project)
@ -19,7 +17,7 @@ CVA5 is licensed under the Solderpad License, Version 2.1 ( http://solderpad.org
## Examples
A zedboard configuration is provided under the examples directory along with tools for running stand-alone applications and providing application level simulation of the system. (See the README in the zedboard directory for details.)
A script to package CVA5 as an IP is available and can be run in Vivado by running `source ./examples/xilinx/package_as_ip.tcl`. A similar script can be executed afterwords to create a system implementing a small hello world application executing from block memory on the Nexys A7 FPGA.
## Publications

58
core/common_components/byte_en_bram.sv
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@ -1,58 +0,0 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module byte_en_bram
import cva5_config::*;
import cva5_types::*;
import riscv_types::*;
#(
parameter LINES = 4096,
parameter preload_file = "",
parameter USE_PRELOAD_FILE = 0
)
(
input logic clk,
input logic[$clog2(LINES)-1:0] addr_a,
input logic en_a,
input logic[XLEN/8-1:0] be_a,
input logic[XLEN-1:0] data_in_a,
output logic[XLEN-1:0] data_out_a,
input logic[$clog2(LINES)-1:0] addr_b,
input logic en_b,
input logic[XLEN/8-1:0] be_b,
input logic[XLEN-1:0] data_in_b,
output logic[XLEN-1:0] data_out_b
);
generate
if(FPGA_VENDOR == XILINX)
xilinx_byte_enable_ram #(LINES, preload_file, USE_PRELOAD_FILE) ram_block (.*);
else
intel_byte_enable_ram #(LINES, preload_file, USE_PRELOAD_FILE) ram_block (.*);
endgenerate
endmodule

70
core/common_components/ram/dual_port_bram.sv
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@ -1,70 +0,0 @@
/*
* Copyright © 2023 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module dual_port_bram
import cva5_config::*;
import cva5_types::*;
import riscv_types::*;
#(
parameter WIDTH = 32,
parameter LINES = 4096
)
(
input logic clk,
input logic en_a,
input logic wen_a,
input logic[$clog2(LINES)-1:0] addr_a,
input logic[WIDTH-1:0] data_in_a,
output logic[WIDTH-1:0] data_out_a,
input logic en_b,
input logic wen_b,
input logic[$clog2(LINES)-1:0] addr_b,
input logic[WIDTH-1:0] data_in_b,
output logic[WIDTH-1:0] data_out_b
);
(* ram_style = "block", ramstyle = "no_rw_check" *) logic [WIDTH-1:0] ram [LINES];
initial ram = '{default: 0};
always_ff @ (posedge clk) begin
if (en_a) begin
if (wen_a)
ram[addr_a] <= data_in_a;
data_out_a <= ram[addr_a];
end
end
always_ff @ (posedge clk) begin
if (en_b) begin
if (wen_b)
ram[addr_b] <= data_in_b;
data_out_b <= ram[addr_b];
end
end
endmodule

9
core/common_components/ram/tdp_ram.sv
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@ -27,7 +27,9 @@ module tdp_ram
parameter NUM_COL = 4, //Number of independently writeable components
parameter COL_WIDTH = 16, //Width the "byte" enable controls
parameter PIPELINE_DEPTH = 1, //Depth of the output pipeline, is latency in clock cycles
parameter CASCADE_DEPTH = 4 //Maximum depth of the memory block cascade
parameter CASCADE_DEPTH = 4, //Maximum depth of the memory block cascade
parameter USE_PRELOAD = 0,
parameter PRELOAD_FILE = ""
)
(
input logic clk,
@ -51,7 +53,10 @@ module tdp_ram
(* cascade_height = CASCADE_DEPTH, ramstyle = "no_rw_check" *) //Higher depths use less resources but are slower
logic[DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
initial mem = '{default: '0};
initial begin
if (USE_PRELOAD)
$readmemh(PRELOAD_FILE, mem, 0);
end
//A read/write
logic[DATA_WIDTH-1:0] a_ram_output;

82
core/common_components/vendor_support/intel/intel_byte_enable_ram.sv
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@ -1,82 +0,0 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module intel_byte_enable_ram
import cva5_config::*;
import riscv_types::*;
import cva5_types::*;
#(
parameter LINES = 8192,
parameter preload_file = "",
parameter USE_PRELOAD_FILE = 0
)
(
input logic clk,
input logic[$clog2(LINES)-1:0] addr_a,
input logic en_a,
input logic[XLEN/8-1:0] be_a,
input logic[XLEN-1:0] data_in_a,
output logic[XLEN-1:0] data_out_a,
input logic[$clog2(LINES)-1:0] addr_b,
input logic en_b,
input logic[XLEN/8-1:0] be_b,
input logic[XLEN-1:0] data_in_b,
output logic[XLEN-1:0] data_out_b
);
(* ramstyle = "no_rw_check" *) logic [3:0][7:0] ram [LINES-1:0];
initial
begin
if(USE_PRELOAD_FILE)
$readmemh(preload_file,ram, 0, LINES-1);
end
always_ff @(posedge clk) begin
if (en_a) begin
if (be_a[0]) ram[addr_a][0] <= data_in_a[7:0];
if (be_a[1]) ram[addr_a][1] <= data_in_a[15:8];
if (be_a[2]) ram[addr_a][2] <= data_in_a[23:16];
if (be_a[3]) ram[addr_a][3] <= data_in_a[31:24];
end
data_out_a <= ram[addr_a];
end
always_ff @(posedge clk) begin
if (en_b) begin
if (be_b[0]) ram[addr_b][0] <= data_in_b[7:0];
if (be_b[1]) ram[addr_b][1] <= data_in_b[15:8];
if (be_b[2]) ram[addr_b][2] <= data_in_b[23:16];
if (be_b[3]) ram[addr_b][3] <= data_in_b[31:24];
end
data_out_b <= ram[addr_b];
end
endmodule

133
core/common_components/vendor_support/xilinx/cva5_wrapper_xilinx.sv
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@ -1,133 +0,0 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module cva5_wrapper_xilinx
import cva5_config::*;
import cva5_types::*;
import l2_config_and_types::*;
(
input logic clk,
input logic rst,
local_memory_interface.master instruction_bram,
local_memory_interface.master data_bram,
l2_requester_interface.master l2,
// AXI SIGNALS - need these to unwrap the interface for packaging //
input logic m_axi_arready,
output logic m_axi_arvalid,
output logic [C_M_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output logic [7:0] m_axi_arlen,
output logic [2:0] m_axi_arsize,
output logic [1:0] m_axi_arburst,
output logic [3:0] m_axi_arcache,
output logic [5:0] m_axi_arid,
//read data
output logic m_axi_rready,
input logic m_axi_rvalid,
input logic [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input logic [1:0] m_axi_rresp,
input logic m_axi_rlast,
input logic [5:0] m_axi_rid,
//Write channel
//write address
input logic m_axi_awready,
output logic m_axi_awvalid,
output logic [C_M_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output logic [7:0] m_axi_awlen,
output logic [2:0] m_axi_awsize,
output logic [1:0] m_axi_awburst,
output logic [3:0] m_axi_awcache,
output logic [5:0] m_axi_awid,
//write data
input logic m_axi_wready,
output logic m_axi_wvalid,
output logic [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output logic [(C_M_AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb,
output logic m_axi_wlast,
//write response
output logic m_axi_bready,
input logic m_axi_bvalid,
input logic [1:0] m_axi_bresp,
input logic [5:0] m_axi_bid
);
//Unused outputs
avalon_interface m_avalon ();
wishbone_interface dwishbone ();
wishbone_interface iwishbone ();
logic timer_interrupt;
logic interrupt;
//AXI interface
axi_interface m_axi();
assign m_axi_arready = m_axi.arready;
assign m_axi_arvalid = m_axi.arvalid;
assign m_axi_araddr = m_axi.araddr;
assign m_axi_arlen = m_axi.arlen;
assign m_axi_arsize = m_axi.arsize;
assign m_axi_arburst = m_axi.arburst;
assign m_axi_arcache = m_axi.arcache;
//assign m_axi_arid = m_axi.arid;
assign m_axi_rready = m_axi.rready;
assign m_axi_rvalid = m_axi.rvalid;
assign m_axi_rdata = m_axi.rdata;
assign m_axi_rresp = m_axi.rresp;
assign m_axi_rlast = m_axi.rlast;
//assign m_axi_rid = m_axi.rid;
assign m_axi_awready = m_axi.awready;
assign m_axi_awvalid = m_axi.awvalid;
assign m_axi_awaddr = m_axi.awaddr;
assign m_axi_awlen = m_axi.awlen;
assign m_axi_awsize = m_axi.awsize;
assign m_axi_awburst = m_axi.awburst;
assign m_axi_awcache = m_axi.awcache;
//assign m_axi_awid = m_axi.awid;
//write data
assign m_axi_wready = m_axi.wready;
assign m_axi_wvalid = m_axi.wvalid;
assign m_axi_wdata = m_axi.wdata;
assign m_axi_wstrb = m_axi.wstrb;
assign m_axi_wlast = m_axi.wlast;
//write response
assign m_axi_bready = m_axi.bready;
assign m_axi_bvalid = m_axi.bvalid;
assign m_axi_bresp = m_axi.bresp;
//assign m_axi_bid = m_axi.bid;
cva5 cpu(.*);
endmodule

87
core/common_components/vendor_support/xilinx/xilinx_byte_enable_ram.sv
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@ -1,87 +0,0 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module xilinx_byte_enable_ram
import cva5_config::*;
import riscv_types::*;
import cva5_types::*;
#(
parameter LINES = 4096,
parameter preload_file = "",
parameter USE_PRELOAD_FILE = 0
)
(
input logic clk,
input logic[$clog2(LINES)-1:0] addr_a,
input logic en_a,
input logic[XLEN/8-1:0] be_a,
input logic[XLEN-1:0] data_in_a,
output logic[XLEN-1:0] data_out_a,
input logic[$clog2(LINES)-1:0] addr_b,
input logic en_b,
input logic[XLEN/8-1:0] be_b,
input logic[XLEN-1:0] data_in_b,
output logic[XLEN-1:0] data_out_b
);
logic [31:0] ram [LINES-1:0];
initial
begin
if(USE_PRELOAD_FILE)
$readmemh(preload_file,ram, 0, LINES-1);
end
generate begin : gen_xilinx_bram
genvar i;
for (i=0; i < 4; i++) begin
always_ff @(posedge clk) begin
if (en_a) begin
if (be_a[i]) begin
ram[addr_a][8*i+:8] <= data_in_a[8*i+:8];
data_out_a[8*i+:8] <= data_in_a[8*i+:8];
end else begin
data_out_a[8*i+:8] <= ram[addr_a][8*i+:8];
end
end
end
end
for (i=0; i < 4; i++) begin
always_ff @(posedge clk) begin
if (en_b) begin
if (be_b[i]) begin
ram[addr_b][8*i+:8] <= data_in_b[8*i+:8];
data_out_b[8*i+:8] <= data_in_b[8*i+:8];
end else begin
data_out_b[8*i+:8] <= ram[addr_b][8*i+:8];
end
end
end
end
end endgenerate
endmodule

4
core/execution_units/csr_unit.sv
View file

@ -332,6 +332,8 @@ module csr_unit
localparam mstatus_t sstatus_mask = '{default:0, mxr:1, sum:1, spp:1, spie:1, sie:1, sd:(CONFIG.INCLUDE_UNIT.FPU), fs:{2{CONFIG.INCLUDE_UNIT.FPU}}};
logic stip_stimecmp;
logic[31:0] sie;
mip_t sip;
mie_t sie_deleg_mask;
localparam mie_t sie_mask = '{default:0, seie:CONFIG.MODES == MSU, stie:CONFIG.MODES == MSU, ssie:CONFIG.MODES == MSU};
localparam mip_t sip_mask = '{default:0, seip:CONFIG.MODES == MSU, stip:CONFIG.MODES == MSU, ssip:CONFIG.MODES == MSU};
@ -722,8 +724,6 @@ endgenerate
logic[31:0] scounteren;
logic[31:0] stimecmp;
logic[31:0] stimecmph;
mip_t sip;
logic[31:0] sie;
localparam logic[31:0] sstateen0 = 0; //The defined behaviour is not used
localparam logic[31:0] sstateen1 = 0;
localparam logic[31:0] sstateen2 = 0;

7
core/execution_units/load_store_unit/dcache_inv.sv
View file

@ -66,6 +66,8 @@ module dcache_inv
AMO_SC,
AMO_RMW
} req_type_t;
req_type_t stage0_type;
req_type_t stage1_type;
typedef struct packed {
logic[31:0] addr;
@ -103,8 +105,6 @@ module dcache_inv
stage1 <= stage0;
end
req_type_t stage0_type;
req_type_t stage1_type;
always_comb begin
if (cbo)
stage0_type = CBO;
@ -240,7 +240,8 @@ module dcache_inv
.ADDR_WIDTH(SCONFIG.LINE_ADDR_W),
.NUM_COL(CONFIG.DCACHE.WAYS),
.COL_WIDTH($bits(tb_entry_t)),
.PIPELINE_DEPTH(0)
.PIPELINE_DEPTH(0),
.USE_PRELOAD(0)
) tagbank (
.a_en(a_en),
.a_wbe(a_wbe),

31
core/execution_units/load_store_unit/dcache_noinv.sv
View file

@ -67,11 +67,25 @@ module dcache_noinv
logic cbo;
} req_t;
typedef enum {
IDLE,
FIRST_CYCLE,
REQUESTING_READ,
FILLING,
UNCACHEABLE_WAITING_READ,
AMO_WRITE
} stage1_t;
//Implementation
req_t stage0;
req_t stage1;
logic stage1_done;
logic stage0_advance_r;
stage1_t current_state;
logic[DB_ADDR_LEN-1:0] db_addr;
logic db_wen;
logic stage1_is_lr;
logic stage1_is_sc;
assign write_outstanding = ((current_state != IDLE) & (~stage1.rnw | stage1.amo)) | mem.write_outstanding;
@ -153,17 +167,16 @@ module dcache_noinv
//Databank
logic[CONFIG.DCACHE.WAYS-1:0][31:0] db_entries;
logic[31:0] db_hit_entry;
logic db_wen;
logic[CONFIG.DCACHE.WAYS-1:0] db_way;
logic[CONFIG.DCACHE.WAYS-1:0][3:0] db_wbe_full;
logic[31:0] db_wdata;
logic[SCONFIG.SUB_LINE_ADDR_W-1:0] word_counter;
always_comb begin
for (int i = 0; i < CONFIG.DCACHE.WAYS; i++)
db_wbe_full[i] = {4{db_way[i]}} & stage1.be;
end
logic[DB_ADDR_LEN-1:0] db_addr;
assign db_addr = current_state == FILLING ? {addr_utils.getTagLineAddr(stage1.addr), word_counter} : addr_utils.getDataLineAddr(stage1.addr);
sdp_ram #(
@ -192,7 +205,6 @@ module dcache_noinv
//Arbiter response
logic correct_word;
logic return_done;
logic[SCONFIG.SUB_LINE_ADDR_W-1:0] word_counter;
assign return_done = mem.rvalid & word_counter == SCONFIG.SUB_LINE_ADDR_W'(CONFIG.DCACHE.LINE_W-1);
assign correct_word = mem.rvalid & word_counter == stage1.addr[2+:SCONFIG.SUB_LINE_ADDR_W];
always_ff @(posedge clk) begin
@ -202,17 +214,7 @@ module dcache_noinv
word_counter <= 0;
end
typedef enum {
IDLE,
FIRST_CYCLE,
REQUESTING_READ,
FILLING,
UNCACHEABLE_WAITING_READ,
AMO_WRITE
} stage1_t;
stage1_t current_state;
stage1_t next_state;
always_ff @(posedge clk) begin
if (rst)
current_state <= IDLE;
@ -336,9 +338,6 @@ module dcache_noinv
end
//AMO
logic stage1_is_lr;
logic stage1_is_sc;
assign stage1_is_lr = stage1.amo & stage1.amo_type == AMO_LR_FN5;
assign stage1_is_sc = stage1.amo & stage1.amo_type == AMO_SC_FN5;

11
core/types_and_interfaces/cva5_config.sv
View file

@ -175,7 +175,7 @@ package cva5_config;
bit INCLUDE_CBO; //Data cache invalidation operations
//Units
units_t INCLUDE_UNIT;
units_t INCLUDE_UNIT; //Value of ALU, LS, BR, and GC ignored
//CSR constants
csr_config_t CSRS;
@ -240,15 +240,12 @@ package cva5_config;
//ISA options
MODES : MSU,
INCLUDE_UNIT : '{
ALU : 1,
LS : 1,
MUL : 1,
DIV : 1,
CSR : 1,
FPU : 1,
CUSTOM : 0,
BR : 1,
GC : 1
default: '0
},
INCLUDE_IFENCE : 1,
INCLUDE_AMO : 0,
@ -345,10 +342,6 @@ package cva5_config;
WB_GROUP : EXAMPLE_WB_GROUP_CONFIG
};
////////////////////////////////////////////////////
//Bus Options
parameter C_M_AXI_ADDR_WIDTH = 32; //Kept as parameter, due to localparam failing with scripted IP packaging
parameter C_M_AXI_DATA_WIDTH = 32; //Kept as parameter, due to localparam failing with scripted IP packaging
////////////////////////////////////////////////////
//ID limit

22
core/types_and_interfaces/external_interfaces.sv
View file

@ -25,7 +25,7 @@ interface axi_interface;
logic arready;
logic arvalid;
logic [C_M_AXI_ADDR_WIDTH-1:0] araddr;
logic [31:0] araddr;
logic [7:0] arlen;
logic [2:0] arsize;
logic [1:0] arburst;
@ -36,7 +36,7 @@ interface axi_interface;
//read data
logic rready;
logic rvalid;
logic [C_M_AXI_DATA_WIDTH-1:0] rdata;
logic [31:0] rdata;
logic [1:0] rresp;
logic rlast;
logic [5:0] rid;
@ -45,7 +45,7 @@ interface axi_interface;
//write address
logic awready;
logic awvalid;
logic [C_M_AXI_ADDR_WIDTH-1:0] awaddr;
logic [31:0] awaddr;
logic [7:0] awlen;
logic [2:0] awsize;
logic [1:0] awburst;
@ -56,8 +56,8 @@ interface axi_interface;
//write data
logic wready;
logic wvalid;
logic [C_M_AXI_DATA_WIDTH-1:0] wdata;
logic [(C_M_AXI_DATA_WIDTH/8)-1:0] wstrb;
logic [31:0] wdata;
logic [3:0] wstrb;
logic wlast;
//write response
@ -150,3 +150,15 @@ interface mem_interface;
modport mem_slave (input request, addr, rlen, rnw, rmw, wbe, wdata, id, output ack, rvalid, rdata, rid, inv, inv_addr, write_outstanding);
endinterface
interface local_memory_interface;
logic[29:0] addr;
logic en;
logic[3:0] be;
logic[31:0] data_in;
logic[31:0] data_out;
modport slave (input addr, en, be, data_in, output data_out);
modport master (output addr, en, be, data_in, input data_out);
endinterface

5
examples/litex/litex_wrapper.sv
View file

@ -130,15 +130,12 @@ module litex_wrapper
//ISA options
MODES : MSU,
INCLUDE_UNIT : '{
ALU : 1,
LS : 1,
MUL : 1,
DIV : 1,
CSR : 1,
FPU : 0,
CUSTOM : 0,
BR : 1,
GC : 1
default: '0
},
INCLUDE_IFENCE : 1,
INCLUDE_AMO : 1,

165
examples/nexys/l1_to_axi.sv
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@ -1,165 +0,0 @@
/*
* Copyright © 2022 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module l1_to_axi
import cva5_config::*;
import riscv_types::*;
import cva5_types::*;
import l2_config_and_types::*;
(
input logic clk,
input logic rst,
l2_requester_interface.slave cpu,
axi_interface.master axi
);
localparam MAX_REQUESTS = 16;
fifo_interface #(.DATA_TYPE(l2_request_t)) request_fifo ();
fifo_interface #(.DATA_TYPE(l2_data_request_t)) data_fifo ();
l2_request_t request;
logic write_request;
logic read_pop;
logic write_pop;
logic aw_complete;
logic w_complete;
logic aw_complete_r;
logic w_complete_r;
////////////////////////////////////////////////////
//Implementation
assign cpu.request_full = request_fifo.full;
assign cpu.data_full = data_fifo.full;
//Repack input attributes
assign request_fifo.data_in = '{
addr : cpu.addr,
rnw : cpu.rnw,
is_amo : cpu.is_amo,
amo_type_or_burst_size : cpu.amo_type_or_burst_size,
sub_id : cpu.sub_id
};
assign request_fifo.push = cpu.request_push;
assign request_fifo.potential_push = cpu.request_push;
assign request_fifo.pop = read_pop | write_pop;
assign request = request_fifo.data_out;
assign data_fifo.push = cpu.wr_data_push;
assign data_fifo.potential_push = cpu.wr_data_push;
assign data_fifo.pop = write_pop;
assign data_fifo.data_in = '{
data : cpu.wr_data,
be : cpu.wr_data_be
};
cva5_fifo #(.DATA_TYPE(l2_request_t), .FIFO_DEPTH(MAX_REQUESTS))
request_fifo_block (
.clk (clk),
.rst (rst),
.fifo (request_fifo)
);
cva5_fifo #(.DATA_TYPE(l2_data_request_t), .FIFO_DEPTH(MAX_REQUESTS))
data_fifo_block (
.clk (clk),
.rst (rst),
.fifo (data_fifo)
);
////////////////////////////////////////////////////
//AXI
localparam MAX_WRITE_IN_FLIGHT = 512;
logic [$clog2(MAX_WRITE_IN_FLIGHT+1)-1:0] write_in_flight_count;
logic [$clog2(MAX_WRITE_IN_FLIGHT+1)-1:0] write_in_flight_count_next;
logic [4:0] burst_size;
assign burst_size = request.amo_type_or_burst_size;
//Read Channel
assign axi.arlen = 8'(burst_size);
assign axi.arburst = (burst_size !=0) ? 2'b01 : '0;// INCR
assign axi.rready = 1; //always ready to receive data
assign axi.arsize = 3'b010;//4 bytes
assign axi.arcache = 4'b0000; //Normal Non-cacheable Non-bufferable
assign axi.arid = 6'(request.sub_id);
assign axi.araddr = {request.addr, 2'b00} & {25'h1FFFFFF, ~burst_size, 2'b00};
assign axi.arvalid = request.rnw & request_fifo.valid & ((request.sub_id[1:0] != L1_DCACHE_ID) | ((request.sub_id[1:0] == L1_DCACHE_ID) & (write_in_flight_count == 0)));
assign read_pop = axi.arvalid & axi.arready;
//Write Channel
assign axi.awlen = '0;
assign axi.awburst = '0;//2'b01;// INCR
assign axi.awsize = 3'b010;//4 bytes
assign axi.bready = 1;
assign axi.awcache = 4'b0000;//Normal Non-cacheable Non-bufferable
assign axi.awaddr = {request.addr, 2'b00};
assign axi.awid = 6'(request.sub_id);
assign write_request = (~request.rnw) & request_fifo.valid & data_fifo.valid;
assign axi.awvalid = write_request & ~aw_complete_r;
assign axi.wdata = data_fifo.data_out.data;
assign axi.wstrb = data_fifo.data_out.be;
assign axi.wvalid = write_request & ~w_complete_r;
assign axi.wlast = axi.wvalid;
assign aw_complete = axi.awvalid & axi.awready;
assign w_complete = axi.wvalid & axi.wready;
always_ff @ (posedge clk) begin
if (rst)
aw_complete_r <= 0;
else
aw_complete_r <= (aw_complete_r | aw_complete) & ~write_pop;
end
always_ff @ (posedge clk) begin
if (rst)
w_complete_r <= 0;
else
w_complete_r <= (w_complete_r | w_complete) & ~write_pop;
end
always_ff @ (posedge clk) begin
if (rst)
write_in_flight_count <= 0;
else
write_in_flight_count <= write_in_flight_count + $clog2(MAX_WRITE_IN_FLIGHT+1)'(write_pop) - $clog2(MAX_WRITE_IN_FLIGHT+1)'(axi.bvalid);
end
assign write_pop = (aw_complete | aw_complete_r) & (w_complete | w_complete_r);
////////////////////////////////////////////////////
//Return Path
//L1 always acks data, no need for rd_data_ack
always_ff @ (posedge clk) begin
cpu.rd_data <= axi.rdata;
cpu.rd_data_valid <= axi.rvalid;
cpu.rd_sub_id <= axi.rid[L2_SUB_ID_W-1:0];
end
endmodule

145
examples/nexys/nexys_config.sv
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@ -1,145 +0,0 @@
/*
* Copyright © 2023 Eric Matthews
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
package nexys_config;
import cva5_config::*;
localparam wb_group_config_t NEXYS_WB_GROUP_CONFIG = '{
0 : '{0: ALU_ID, default : NON_WRITEBACK_ID},
1 : '{0: LS_ID, default : NON_WRITEBACK_ID},
2 : '{0: MUL_ID, 1: DIV_ID, 2: CSR_ID, 3: FPU_ID, 4: CUSTOM_ID, default : NON_WRITEBACK_ID},
default : '{default : NON_WRITEBACK_ID}
};
localparam cpu_config_t NEXYS_CONFIG = '{
//ISA options
MODES : MSU,
INCLUDE_UNIT : '{
ALU : 1,
LS : 1,
MUL : 1,
DIV : 1,
CSR : 1,
FPU : 1,
CUSTOM : 0,
BR : 1,
GC : 1
},
INCLUDE_IFENCE : 0,
INCLUDE_AMO : 0,
INCLUDE_CBO : 0,
//CSR constants
CSRS : '{
MACHINE_IMPLEMENTATION_ID : 0,
CPU_ID : 0,
RESET_VEC : 32'h80000000,
RESET_TVEC : 32'h00000000,
MCONFIGPTR : '0,
INCLUDE_ZICNTR : 1,
INCLUDE_ZIHPM : 1,
INCLUDE_SSTC : 1,
INCLUDE_SMSTATEEN : 1
},
//Memory Options
SQ_DEPTH : 8,
INCLUDE_FORWARDING_TO_STORES : 1,
AMO_UNIT : '{
LR_WAIT : 32,
RESERVATION_WORDS : 8 //Must be the same size as the DCACHE line width
},
INCLUDE_ICACHE : 1,
ICACHE_ADDR : '{
L : 32'h80000000,
H : 32'h87FFFFFF
},
ICACHE : '{
LINES : 256,
LINE_W : 8,
WAYS : 2,
USE_EXTERNAL_INVALIDATIONS : 0,
USE_NON_CACHEABLE : 0,
NON_CACHEABLE : '{
L : 32'h88000000,
H : 32'h8FFFFFFF
}
},
ITLB : '{
WAYS : 2,
DEPTH : 64
},
INCLUDE_DCACHE : 1,
DCACHE_ADDR : '{
L : 32'h80000000,
H : 32'h8FFFFFFF
},
DCACHE : '{
LINES : 512,
LINE_W : 8,
WAYS : 1,
USE_EXTERNAL_INVALIDATIONS : 0,
USE_NON_CACHEABLE : 1,
NON_CACHEABLE : '{
L : 32'h88000000,
H : 32'h8FFFFFFF
}
},
DTLB : '{
WAYS : 2,
DEPTH : 64
},
INCLUDE_ILOCAL_MEM : 0,
ILOCAL_MEM_ADDR : '{
L : 32'h80000000,
H : 32'h8FFFFFFF
},
INCLUDE_DLOCAL_MEM : 0,
DLOCAL_MEM_ADDR : '{
L : 32'h80000000,
H : 32'h8FFFFFFF
},
INCLUDE_IBUS : 0,
IBUS_ADDR : '{
L : 32'h00000000,
H : 32'hFFFFFFFF
},
INCLUDE_PERIPHERAL_BUS : 1,
PERIPHERAL_BUS_ADDR : '{
L : 32'h60000000,
H : 32'h6FFFFFFF
},
PERIPHERAL_BUS_TYPE : AXI_BUS,
//Branch Predictor Options
INCLUDE_BRANCH_PREDICTOR : 1,
BP : '{
WAYS : 2,
ENTRIES : 512,
RAS_ENTRIES : 8
},
//Writeback Options
NUM_WB_GROUPS : 3,
WB_GROUP : NEXYS_WB_GROUP_CONFIG
};
endpackage

141
examples/nexys/nexys_wrapper.sv
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@ -1,141 +0,0 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module nexys_wrapper
import cva5_config::*;
import cva5_types::*;
import l2_config_and_types::*;
import nexys_config::*;
(
input logic clk,
input logic rst,
// AXI SIGNALS - need these to unwrap the interface for packaging //
input logic m_axi_arready,
output logic m_axi_arvalid,
output logic [31:0] m_axi_araddr,
output logic [7:0] m_axi_arlen,
output logic [2:0] m_axi_arsize,
output logic [1:0] m_axi_arburst,
output logic [3:0] m_axi_arcache,
output logic [5:0] m_axi_arid,
//read data
output logic m_axi_rready,
input logic m_axi_rvalid,
input logic [31:0] m_axi_rdata,
input logic [1:0] m_axi_rresp,
input logic m_axi_rlast,
input logic [5:0] m_axi_rid,
//Write channel
//write address
input logic m_axi_awready,
output logic m_axi_awvalid,
output logic [31:0] m_axi_awaddr,
output logic [7:0] m_axi_awlen,
output logic [2:0] m_axi_awsize,
output logic [1:0] m_axi_awburst,
output logic [3:0] m_axi_awcache,
output logic [5:0] m_axi_awid,
//write data
input logic m_axi_wready,
output logic m_axi_wvalid,
output logic [31:0] m_axi_wdata,
output logic [3:0] m_axi_wstrb,
output logic m_axi_wlast,
//write response
output logic m_axi_bready,
input logic m_axi_bvalid,
input logic [1:0] m_axi_bresp,
input logic [5:0] m_axi_bid
);
//Unused outputs
local_memory_interface instruction_bram ();
local_memory_interface data_bram ();
avalon_interface m_avalon ();
wishbone_interface dwishbone ();
wishbone_interface iwishbone ();
axi_interface m_axi ();
interrupt_t m_interrupt;
interrupt_t s_interrupt;
//L2 and AXI
l2_requester_interface l2 ();
axi_interface axi ();
logic rst_r1, rst_r2;
assign axi.arready = m_axi_arready;
assign m_axi_arvalid = axi.arvalid;
assign m_axi_araddr = axi.araddr;
assign m_axi_arlen = axi.arlen;
assign m_axi_arsize = axi.arsize;
assign m_axi_arburst = axi.arburst;
assign m_axi_arcache = axi.arcache;
assign m_axi_arid = axi.arid;
assign m_axi_rready = axi.rready;
assign axi.rvalid = m_axi_rvalid;
assign axi.rdata = m_axi_rdata;
assign axi.rresp = m_axi_rresp;
assign axi.rlast = m_axi_rlast;
assign axi.rid = m_axi_rid;
assign axi.awready = m_axi_awready;
assign m_axi_awvalid = axi.awvalid;
assign m_axi_awaddr = axi.awaddr;
assign m_axi_awlen = axi.awlen;
assign m_axi_awsize = axi.awsize;
assign m_axi_awburst = axi.awburst;
assign m_axi_awcache = axi.awcache;
assign m_axi_awid = axi.awid;
//write data
assign axi.wready = m_axi_wready;
assign m_axi_wvalid = axi.wvalid;
assign m_axi_wdata = axi.wdata;
assign m_axi_wstrb = axi.wstrb;
assign m_axi_wlast = axi.wlast;
//write response
assign m_axi_bready = axi.bready;
assign axi.bvalid = m_axi_bvalid;
assign axi.bresp = m_axi_bresp;
assign axi.bid = m_axi_bid;
always_ff @ (posedge clk) begin
rst_r1 <= rst;
rst_r2 <= rst_r1;
end
l1_to_axi arb(.*, .cpu(l2), .axi(axi));
cva5 #(.CONFIG(NEXYS_CONFIG)) cpu(.rst(rst_r2), .*);
endmodule

88
examples/nexys/scripts/cva5-ip-core-base.tcl
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@ -1,88 +0,0 @@
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir [file dirname [info script]]
# Set the project name
set _xil_proj_name_ "cva5_nexys_wrapper"
set sources_dir $origin_dir/../../../
# Create project
create_project ${_xil_proj_name_} $origin_dir/${_xil_proj_name_}
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [current_project]
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_language" -value "Verilog" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
#import sources needed for blackbox packaging
import_files -norecurse $sources_dir/examples/nexys/nexys_config.sv
import_files -norecurse $sources_dir/examples/nexys/nexys_wrapper.sv
import_files -norecurse $sources_dir/l2_arbiter/l2_external_interfaces.sv
import_files -norecurse $sources_dir/local_memory/local_memory_interface.sv
import_files -norecurse $sources_dir/core/types_and_interfaces/external_interfaces.sv
import_files -norecurse $sources_dir/core/types_and_interfaces/cva5_config.sv
import_files -norecurse $sources_dir/core/types_and_interfaces/riscv_types.sv
import_files -norecurse $sources_dir/core/types_and_interfaces/cva5_types.sv
import_files -norecurse $sources_dir/core/types_and_interfaces/csr_types.sv
import_files -norecurse $sources_dir/l2_arbiter/l2_config_and_types.sv
# Set IP repository paths
set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/${_xil_proj_name_}"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "nexys_wrapper" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_file" -value " ${sources_dir}/examples/nexys/nexys_wrapper.sv" -objects $obj
############## Initial IP Packaging
ipx::package_project -import_files -force -root_dir $proj_dir
update_compile_order -fileset sources_1
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
# To set the axi interface as aximm and port map all the signals over #
##### Naming
set_property name CVA5 [ipx::current_core]
set_property display_name CVA5_NEXYS7 [ipx::current_core]
set_property description CVA5_NEXYS7 [ipx::current_core]
set_property vendor {} [ipx::current_core]
set_property vendor user [ipx::current_core]
##### Re-Adding of project files
set_property ip_repo_paths $sources_dir/${_xil_proj_name_} [current_project]
current_project $_xil_proj_name_
update_ip_catalog
import_files -force -fileset [get_filesets sources_1] $sources_dir/core
import_files -force -fileset [get_filesets sources_1] $sources_dir/l2_arbiter
import_files -force -fileset [get_filesets sources_1] $sources_dir/local_memory
import_files -fileset [get_filesets sources_1] $sources_dir/examples/nexys/l1_to_axi.sv
############## Re-packaging of core
update_compile_order -fileset sources_1
ipx::merge_project_changes files [ipx::current_core]
set_property core_revision 1 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
current_project ${_xil_proj_name_}
set_property "ip_repo_paths" "[file normalize "$origin_dir/${_xil_proj_name_} "]" $obj
update_ip_catalog -rebuild

18
examples/nexys/scripts/manual_pin_assignments.xdc
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@ -1,18 +0,0 @@
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {LED[0]}]
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {LED[1]}]
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {LED[2]}]
set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {LED[3]}]
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {LED[4]}]
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {LED[5]}]
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {LED[6]}]
set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {LED[7]}]
set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {LED[8]}]
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {LED[9]}]
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {LED[10]}]
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {LED[11]}]
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {LED[12]}]
set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {LED[13]}]
set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {LED[14]}]
set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {LED[15]}]

510
examples/nexys/scripts/system.tcl
View file

@ -1,510 +0,0 @@
################################################################
# This is a generated script based on design: system
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2022.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source system_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project cva5-competition-baseline cva5-competition-baseline -part xc7a100tcsg324-1
set_property BOARD_PART digilentinc.com:nexys-a7-100t:part0:1.2 [current_project]
} else {
common::send_gid_msg -ssname BD::TCL -id 2100 -severity "ERROR" "Open project must be closed before running."
return -1
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name system
add_files -fileset constrs_1 -norecurse $script_folder/manual_pin_assignments.xdc
set_property ip_repo_paths $script_folder/cva5_nexys_wrapper [current_project]
update_ip_catalog
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
user:user:CVA5:1.0\
xilinx.com:ip:axi_gpio:2.0\
xilinx.com:ip:axi_uart16550:2.0\
xilinx.com:ip:clk_wiz:6.0\
xilinx.com:ip:mdm:3.2\
xilinx.com:ip:mig_7series:4.2\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:xlslice:1.0\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# MIG PRJ FILE TCL PROCs
##################################################################
proc write_mig_file_system_mig_7series_0_0 { str_mig_prj_filepath } {
file mkdir [ file dirname "$str_mig_prj_filepath" ]
set mig_prj_file [open $str_mig_prj_filepath w+]
puts $mig_prj_file {<?xml version="1.0" encoding="UTF-8" standalone="no" ?>}
puts $mig_prj_file {<Project NoOfControllers="1">}
puts $mig_prj_file { }
puts $mig_prj_file {<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->}
puts $mig_prj_file { <ModuleName>system_mig_7series_0_0</ModuleName>}
puts $mig_prj_file { <dci_inouts_inputs>1</dci_inouts_inputs>}
puts $mig_prj_file { <dci_inputs>1</dci_inputs>}
puts $mig_prj_file { <Debug_En>OFF</Debug_En>}
puts $mig_prj_file { <DataDepth_En>1024</DataDepth_En>}
puts $mig_prj_file { <LowPower_En>ON</LowPower_En>}
puts $mig_prj_file { <XADC_En>Enabled</XADC_En>}
puts $mig_prj_file { <TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>}
puts $mig_prj_file { <Version>4.2</Version>}
puts $mig_prj_file { <SystemClock>No Buffer</SystemClock>}
puts $mig_prj_file { <ReferenceClock>No Buffer</ReferenceClock>}
puts $mig_prj_file { <SysResetPolarity>ACTIVE LOW</SysResetPolarity>}
puts $mig_prj_file { <BankSelectionFlag>FALSE</BankSelectionFlag>}
puts $mig_prj_file { <InternalVref>1</InternalVref>}
puts $mig_prj_file { <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>}
puts $mig_prj_file { <dci_cascade>0</dci_cascade>}
puts $mig_prj_file { <Controller number="0">}
puts $mig_prj_file { <MemoryDevice>DDR2_SDRAM/Components/MT47H64M16HR-25E</MemoryDevice>}
puts $mig_prj_file { <TimePeriod>5000</TimePeriod>}
puts $mig_prj_file { <VccAuxIO>1.8V</VccAuxIO>}
puts $mig_prj_file { <PHYRatio>2:1</PHYRatio>}
puts $mig_prj_file { <InputClkFreq>100</InputClkFreq>}
puts $mig_prj_file { <UIExtraClocks>1</UIExtraClocks>}
puts $mig_prj_file { <MMCM_VCO>1200</MMCM_VCO>}
puts $mig_prj_file { <MMCMClkOut0> 6.000</MMCMClkOut0>}
puts $mig_prj_file { <MMCMClkOut1>1</MMCMClkOut1>}
puts $mig_prj_file { <MMCMClkOut2>1</MMCMClkOut2>}
puts $mig_prj_file { <MMCMClkOut3>1</MMCMClkOut3>}
puts $mig_prj_file { <MMCMClkOut4>1</MMCMClkOut4>}
puts $mig_prj_file { <DataWidth>16</DataWidth>}
puts $mig_prj_file { <DeepMemory>1</DeepMemory>}
puts $mig_prj_file { <DataMask>1</DataMask>}
puts $mig_prj_file { <ECC>Disabled</ECC>}
puts $mig_prj_file { <Ordering>Strict</Ordering>}
puts $mig_prj_file { <BankMachineCnt>4</BankMachineCnt>}
puts $mig_prj_file { <CustomPart>FALSE</CustomPart>}
puts $mig_prj_file { <NewPartName/>}
puts $mig_prj_file { <RowAddress>13</RowAddress>}
puts $mig_prj_file { <ColAddress>10</ColAddress>}
puts $mig_prj_file { <BankAddress>3</BankAddress>}
puts $mig_prj_file { <C0_MEM_SIZE>134217728</C0_MEM_SIZE>}
puts $mig_prj_file { <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>}
puts $mig_prj_file { <PinSelection>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M4" SLEW="" VCCAUX_IO="" name="ddr2_addr[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R2" SLEW="" VCCAUX_IO="" name="ddr2_addr[10]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="K5" SLEW="" VCCAUX_IO="" name="ddr2_addr[11]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N6" SLEW="" VCCAUX_IO="" name="ddr2_addr[12]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P4" SLEW="" VCCAUX_IO="" name="ddr2_addr[1]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr2_addr[2]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr2_addr[3]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="L3" SLEW="" VCCAUX_IO="" name="ddr2_addr[4]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr2_addr[5]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr2_addr[6]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N1" SLEW="" VCCAUX_IO="" name="ddr2_addr[7]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr2_addr[8]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr2_addr[9]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr2_ba[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P3" SLEW="" VCCAUX_IO="" name="ddr2_ba[1]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr2_ba[2]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr2_cas_n"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="L5" SLEW="" VCCAUX_IO="" name="ddr2_ck_n[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="L6" SLEW="" VCCAUX_IO="" name="ddr2_ck_p[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr2_cke[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr2_cs_n[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr2_dm[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr2_dm[1]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R7" SLEW="" VCCAUX_IO="" name="ddr2_dq[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr2_dq[10]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U4" SLEW="" VCCAUX_IO="" name="ddr2_dq[11]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr2_dq[12]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T4" SLEW="" VCCAUX_IO="" name="ddr2_dq[13]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V1" SLEW="" VCCAUX_IO="" name="ddr2_dq[14]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T3" SLEW="" VCCAUX_IO="" name="ddr2_dq[15]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V6" SLEW="" VCCAUX_IO="" name="ddr2_dq[1]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R8" SLEW="" VCCAUX_IO="" name="ddr2_dq[2]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U7" SLEW="" VCCAUX_IO="" name="ddr2_dq[3]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr2_dq[4]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr2_dq[5]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr2_dq[6]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr2_dq[7]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr2_dq[8]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr2_dq[9]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr2_dqs_n[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr2_dqs_n[1]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="U9" SLEW="" VCCAUX_IO="" name="ddr2_dqs_p[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr2_dqs_p[1]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr2_odt[0]"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N4" SLEW="" VCCAUX_IO="" name="ddr2_ras_n"/>}
puts $mig_prj_file { <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr2_we_n"/>}
puts $mig_prj_file { </PinSelection>}
puts $mig_prj_file { <System_Control>}
puts $mig_prj_file { <Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>}
puts $mig_prj_file { <Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>}
puts $mig_prj_file { <Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>}
puts $mig_prj_file { </System_Control>}
puts $mig_prj_file { <TimingParameters>}
puts $mig_prj_file { <Parameters tfaw="45" tras="40" trcd="15" trefi="7.8" trfc="127.5" trp="12.5" trrd="10" trtp="7.5" twtr="7.5"/>}
puts $mig_prj_file { </TimingParameters>}
puts $mig_prj_file { <mrBurstLength name="Burst Length">8</mrBurstLength>}
puts $mig_prj_file { <mrBurstType name="Burst Type">Sequential</mrBurstType>}
puts $mig_prj_file { <mrCasLatency name="CAS Latency">3</mrCasLatency>}
puts $mig_prj_file { <mrMode name="Mode">Normal</mrMode>}
puts $mig_prj_file { <mrDllReset name="DLL Reset">No</mrDllReset>}
puts $mig_prj_file { <mrPdMode name="PD Mode">Fast exit</mrPdMode>}
puts $mig_prj_file { <mrWriteRecovery name="Write Recovery">3</mrWriteRecovery>}
puts $mig_prj_file { <emrDllEnable name="DLL Enable">Enable-Normal</emrDllEnable>}
puts $mig_prj_file { <emrOutputDriveStrength name="Output Drive Strength">Fullstrength</emrOutputDriveStrength>}
puts $mig_prj_file { <emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>}
puts $mig_prj_file { <emrCKSelection name="Memory Clock Selection">1</emrCKSelection>}
puts $mig_prj_file { <emrRTT name="RTT (nominal) - ODT">50ohms</emrRTT>}
puts $mig_prj_file { <emrPosted name="Additive Latency (AL)">0</emrPosted>}
puts $mig_prj_file { <emrOCD name="OCD Operation">OCD Exit</emrOCD>}
puts $mig_prj_file { <emrDQS name="DQS# Enable">Enable</emrDQS>}
puts $mig_prj_file { <emrRDQS name="RDQS Enable">Disable</emrRDQS>}
puts $mig_prj_file { <emrOutputs name="Outputs">Enable</emrOutputs>}
puts $mig_prj_file { <PortInterface>AXI</PortInterface>}
puts $mig_prj_file { <AXIParameters>}
puts $mig_prj_file { <C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>}
puts $mig_prj_file { <C0_S_AXI_ADDR_WIDTH>27</C0_S_AXI_ADDR_WIDTH>}
puts $mig_prj_file { <C0_S_AXI_DATA_WIDTH>32</C0_S_AXI_DATA_WIDTH>}
puts $mig_prj_file { <C0_S_AXI_ID_WIDTH>7</C0_S_AXI_ID_WIDTH>}
puts $mig_prj_file { <C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>}
puts $mig_prj_file { </AXIParameters>}
puts $mig_prj_file { </Controller>}
puts $mig_prj_file {</Project>}
close $mig_prj_file
}
# End of write_mig_file_system_mig_7series_0_0()
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set ddr2_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr2_sdram ]
set dip_switches_16bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 dip_switches_16bits ]
set rgb_led [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 rgb_led ]
set usb_uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 usb_uart ]
# Create ports
set LED [ create_bd_port -dir O -from 15 -to 0 -type data LED ]
set reset [ create_bd_port -dir I -type rst reset ]
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_LOW} \
] $reset
set sys_clock [ create_bd_port -dir I -type clk -freq_hz 100000000 sys_clock ]
set_property -dict [ list \
CONFIG.PHASE {0.0} \
] $sys_clock
# Create instance: CVA5_0, and set properties
set CVA5_0 [ create_bd_cell -type ip -vlnv user:user:CVA5:1.0 CVA5_0 ]
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
set_property -dict [ list \
CONFIG.C_ALL_OUTPUTS_2 {1} \
CONFIG.C_DOUT_DEFAULT_2 {0x00000001} \
CONFIG.C_GPIO2_WIDTH {16} \
CONFIG.C_IS_DUAL {1} \
CONFIG.GPIO2_BOARD_INTERFACE {Custom} \
CONFIG.GPIO_BOARD_INTERFACE {dip_switches_16bits} \
CONFIG.USE_BOARD_FLOW {true} \
] $axi_gpio_0
# Create instance: axi_gpio_1, and set properties
set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
set_property -dict [ list \
CONFIG.GPIO_BOARD_INTERFACE {rgb_led} \
CONFIG.USE_BOARD_FLOW {true} \
] $axi_gpio_1
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {4} \
CONFIG.NUM_SI {2} \
CONFIG.S00_HAS_DATA_FIFO {2} \
CONFIG.S01_HAS_DATA_FIFO {2} \
CONFIG.STRATEGY {2} \
] $axi_interconnect_0
# Create instance: axi_uart16550_0, and set properties
set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ]
set_property -dict [ list \
CONFIG.UART_BOARD_INTERFACE {usb_uart} \
CONFIG.USE_BOARD_FLOW {true} \
] $axi_uart16550_0
# Create instance: clk_wiz_0, and set properties
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
set_property -dict [ list \
CONFIG.CLK_IN1_BOARD_INTERFACE {sys_clock} \
CONFIG.RESET_BOARD_INTERFACE {reset} \
CONFIG.RESET_PORT {resetn} \
CONFIG.RESET_TYPE {ACTIVE_LOW} \
CONFIG.USE_LOCKED {false} \
] $clk_wiz_0
# Create instance: mdm_1, and set properties
set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]
set_property -dict [ list \
CONFIG.C_ADDR_SIZE {32} \
CONFIG.C_DBG_MEM_ACCESS {1} \
CONFIG.C_MB_DBG_PORTS {0} \
CONFIG.C_M_AXI_ADDR_WIDTH {32} \
] $mdm_1
# Create instance: mig_7series_0, and set properties
set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 mig_7series_0 ]
# Generate the PRJ File for MIG
set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $mig_7series_0 ] ] ]
set str_mig_file_name mig_b.prj
set str_mig_file_path ${str_mig_folder}/${str_mig_file_name}
write_mig_file_system_mig_7series_0_0 $str_mig_file_path
set_property -dict [ list \
CONFIG.BOARD_MIG_PARAM {ddr2_sdram} \
CONFIG.RESET_BOARD_INTERFACE {reset} \
CONFIG.XML_INPUT_FILE {mig_b.prj} \
] $mig_7series_0
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
# Create instance: xlslice_0, and set properties
set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
set_property -dict [ list \
CONFIG.DIN_WIDTH {16} \
] $xlslice_0
# Create interface connections
connect_bd_intf_net -intf_net CVA5_0_m_axi [get_bd_intf_pins CVA5_0/m_axi] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports dip_switches_16bits] [get_bd_intf_pins axi_gpio_0/GPIO]
connect_bd_intf_net -intf_net axi_gpio_1_GPIO [get_bd_intf_ports rgb_led] [get_bd_intf_pins axi_gpio_1/GPIO]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins mig_7series_0/S_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins axi_uart16550_0/S_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
connect_bd_intf_net -intf_net axi_uart16550_0_UART [get_bd_intf_ports usb_uart] [get_bd_intf_pins axi_uart16550_0/UART]
connect_bd_intf_net -intf_net mdm_1_M_AXI [get_bd_intf_pins axi_interconnect_0/S01_AXI] [get_bd_intf_pins mdm_1/M_AXI]
connect_bd_intf_net -intf_net mig_7series_0_DDR2 [get_bd_intf_ports ddr2_sdram] [get_bd_intf_pins mig_7series_0/DDR2]
# Create port connections
connect_bd_net -net axi_gpio_0_gpio2_io_o [get_bd_ports LED] [get_bd_pins axi_gpio_0/gpio2_io_o] [get_bd_pins xlslice_0/Din]
connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins mig_7series_0/sys_clk_i]
connect_bd_net -net mdm_1_Debug_SYS_Rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins proc_sys_reset_0/mb_debug_sys_rst]
connect_bd_net -net mig_7series_0_ui_addn_clk_0 [get_bd_pins mig_7series_0/clk_ref_i] [get_bd_pins mig_7series_0/ui_addn_clk_0]
connect_bd_net -net mig_7series_0_ui_clk [get_bd_pins CVA5_0/clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins mdm_1/M_AXI_ACLK] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in]
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins clk_wiz_0/resetn] [get_bd_pins mig_7series_0/sys_rst]
connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins mdm_1/M_AXI_ARESETN] [get_bd_pins mig_7series_0/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
connect_bd_net -net sys_clock_1 [get_bd_ports sys_clock] [get_bd_pins clk_wiz_0/clk_in1]
connect_bd_net -net xlslice_0_Dout [get_bd_pins CVA5_0/rst] [get_bd_pins xlslice_0/Dout]
# Create address segments
assign_bd_address -offset 0x88100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces CVA5_0/m_axi] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force
assign_bd_address -offset 0x88200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces CVA5_0/m_axi] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] -force
assign_bd_address -offset 0x88000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces CVA5_0/m_axi] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force
assign_bd_address -offset 0x80000000 -range 0x08000000 -target_address_space [get_bd_addr_spaces CVA5_0/m_axi] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force
assign_bd_address -offset 0x88100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces mdm_1/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force
assign_bd_address -offset 0x88200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces mdm_1/Data] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] -force
assign_bd_address -offset 0x88000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces mdm_1/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force
assign_bd_address -offset 0x80000000 -range 0x08000000 -target_address_space [get_bd_addr_spaces mdm_1/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
make_wrapper -files [get_files $script_folder/cva5-competition-baseline/cva5-competition-baseline.srcs/sources_1/bd/system/system.bd] -top
add_files -norecurse $script_folder/cva5-competition-baseline/cva5-competition-baseline.gen/sources_1/bd/system/hdl/system_wrapper.v
update_compile_order -fileset sources_1

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/*
* Copyright © 2024 Chris Keilbart
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Chris Keilbart <ckeilbar@sfu.ca>
*/
#include <stdio.h>
#include <stdatomic.h>
//Needed to "sleep" for the correct duration
#define MHZ 100
static void usleep(unsigned usecs) {
unsigned int counter = usecs * MHZ;
counter /= 2; //Two instructions per loop body; decrement and compare
do {
atomic_thread_fence(memory_order_relaxed); //This prevents the loop from being optimized away but doesn't do anything
} while (counter-- > 0); //Assumes that a tight add and branch loop can be sustained at 1 IPC
}
//Example program to run on CVA5, assumes running at 100 MHz
//The accompanying mem.mif file is the corresponding executable in hexadecimal format
//It was compiled targetting RV32IM with a 4KB memory size, and a uart_putc function supporting the AXI UART Lite AMD IP
int main(void) {
while(1) {
puts("Hello World!");
usleep(1000*1000);
}
return 0;
}

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/*
* Copyright © 2024 Chris Keilbart
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Chris Keilbart <ckeilbar@sfu.ca>
*/
module cva5_top
#(
parameter LOCAL_MEM = "mem.mif",
parameter WORDS = 1024
)
(
input clk,
input rstn, //Synchronous active low
//Peripheral AXI4-Lite bus
//AR
input m_axi_arready,
output m_axi_arvalid,
output [31:0] m_axi_araddr,
//R
output m_axi_rready,
input m_axi_rvalid,
input [31:0] m_axi_rdata,
input [1:0] m_axi_rresp,
//AW
input m_axi_awready,
output m_axi_awvalid,
output [31:0] m_axi_awaddr,
//W
input m_axi_wready,
output m_axi_wvalid,
output [31:0] m_axi_wdata,
output [3:0] m_axi_wstrb,
//write response
output m_axi_bready,
input m_axi_bvalid,
input [1:0] m_axi_bresp
);
cva5_wrapper #(.LOCAL_MEM(LOCAL_MEM), .WORDS(WORDS)) cva5_inst(
.clk(clk),
.rstn(rstn),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_araddr(m_axi_araddr),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bresp(m_axi_bresp)
);
endmodule

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/*
* Copyright © 2024 Chris Keilbart
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Chris Keilbart <ckeilbar@sfu.ca>
*/
module cva5_wrapper
import cva5_config::*;
import cva5_types::*;
#(
parameter string LOCAL_MEM = "mem.mif",
parameter int unsigned WORDS = 1024
)
(
input logic clk,
input logic rstn, //Synchronous active low
//Peripheral AXI bus
//AR
input logic m_axi_arready,
output logic m_axi_arvalid,
output logic [31:0] m_axi_araddr,
//R
output logic m_axi_rready,
input logic m_axi_rvalid,
input logic [31:0] m_axi_rdata,
input logic [1:0] m_axi_rresp,
//AW
input logic m_axi_awready,
output logic m_axi_awvalid,
output logic [31:0] m_axi_awaddr,
//W
input logic m_axi_wready,
output logic m_axi_wvalid,
output logic [31:0] m_axi_wdata,
output logic [3:0] m_axi_wstrb,
//write response
output logic m_axi_bready,
input logic m_axi_bvalid,
input logic [1:0] m_axi_bresp
);
//CPU connections
local_memory_interface data_bram();
local_memory_interface instruction_bram();
axi_interface m_axi();
avalon_interface m_avalon(); //Unused
wishbone_interface dwishbone(); //Unused
wishbone_interface iwishbone(); //Unused
mem_interface mem();
logic[63:0] mtime;
interrupt_t s_interrupt; //Unused
interrupt_t m_interrupt; //Unused
////////////////////////////////////////////////////
//Implementation
//Instantiates a CVA5 processor using local memory
//Program start address 0x8000_0000
//Local memory space from 0x8000_0000 through 0x80FF_FFFF
//Peripheral bus from 0x6000_0000 through 0x6FFF_FFFF
localparam wb_group_config_t WB_CPU_CONFIG = '{
0 : '{0: ALU_ID, default : NON_WRITEBACK_ID},
1 : '{0: LS_ID, default : NON_WRITEBACK_ID},
2 : '{0: MUL_ID, 1: DIV_ID, 2: CSR_ID, 3: FPU_ID, 4: CUSTOM_ID, default : NON_WRITEBACK_ID},
default : '{default : NON_WRITEBACK_ID}
};
localparam cpu_config_t CPU_CONFIG = '{
//ISA options
MODES : M,
INCLUDE_UNIT : '{
MUL : 1,
DIV : 1,
CSR : 1,
FPU : 0,
CUSTOM : 0,
default: '0
},
INCLUDE_IFENCE : 0,
INCLUDE_AMO : 0,
INCLUDE_CBO : 0,
//CSR constants
CSRS : '{
MACHINE_IMPLEMENTATION_ID : 0,
CPU_ID : 0,
RESET_VEC : 32'h80000000,
RESET_TVEC : 32'h00000000,
MCONFIGPTR : '0,
INCLUDE_ZICNTR : 1,
INCLUDE_ZIHPM : 0,
INCLUDE_SSTC : 0,
INCLUDE_SMSTATEEN : 0
},
//Memory Options
SQ_DEPTH : 4,
INCLUDE_FORWARDING_TO_STORES : 1,
AMO_UNIT : '{
LR_WAIT : 32,
RESERVATION_WORDS : 8
},
INCLUDE_ICACHE : 0,
ICACHE_ADDR : '{
L: 32'h80000000,
H: 32'h8FFFFFFF
},
ICACHE : '{
LINES : 512,
LINE_W : 4,
WAYS : 2,
USE_EXTERNAL_INVALIDATIONS : 0,
USE_NON_CACHEABLE : 0,
NON_CACHEABLE : '{
L: 32'h70000000,
H: 32'h7FFFFFFF
}
},
ITLB : '{
WAYS : 2,
DEPTH : 64
},
INCLUDE_DCACHE : 0,
DCACHE_ADDR : '{
L: 32'h80000000,
H: 32'h8FFFFFFF
},
DCACHE : '{
LINES : 512,
LINE_W : 4,
WAYS : 2,
USE_EXTERNAL_INVALIDATIONS : 0,
USE_NON_CACHEABLE : 0,
NON_CACHEABLE : '{
L: 32'h70000000,
H: 32'h7FFFFFFF
}
},
DTLB : '{
WAYS : 2,
DEPTH : 64
},
INCLUDE_ILOCAL_MEM : 1,
ILOCAL_MEM_ADDR : '{
L : 32'h80000000,
H : 32'h80FFFFFF
},
INCLUDE_DLOCAL_MEM : 1,
DLOCAL_MEM_ADDR : '{
L : 32'h80000000,
H : 32'h80FFFFFF
},
INCLUDE_IBUS : 0,
IBUS_ADDR : '{
L : 32'h60000000,
H : 32'h6FFFFFFF
},
INCLUDE_PERIPHERAL_BUS : 1,
PERIPHERAL_BUS_ADDR : '{
L : 32'h60000000,
H : 32'h6FFFFFFF
},
PERIPHERAL_BUS_TYPE : AXI_BUS,
//Branch Predictor Options
INCLUDE_BRANCH_PREDICTOR : 1,
BP : '{
WAYS : 2,
ENTRIES : 512,
RAS_ENTRIES : 8
},
//Writeback Options
NUM_WB_GROUPS : 3,
WB_GROUP : WB_CPU_CONFIG
};
logic rst;
assign rst = ~rstn;
cva5 #(.CONFIG(CPU_CONFIG)) cpu(.*);
always_ff @(posedge clk) begin
if (rst)
mtime <= '0;
else
mtime <= mtime + 1;
end
assign s_interrupt = '{default: '0};
assign m_interrupt = '{default: '0};
//AXI peripheral mapping; ID widths are missmatched but unused
assign m_axi.arready = m_axi_arready;
assign m_axi_arvalid = m_axi.arvalid;
assign m_axi_araddr = m_axi.araddr;
assign m_axi_rready = m_axi.rready;
assign m_axi.rvalid = m_axi_rvalid;
assign m_axi.rdata = m_axi_rdata;
assign m_axi.rresp = m_axi_rresp;
assign m_axi.rid = 6'b0;
assign m_axi.awready = m_axi_awready;
assign m_axi_awvalid = m_axi.awvalid;
assign m_axi_awaddr = m_axi.awaddr;
assign m_axi.wready = m_axi_wready;
assign m_axi_wvalid = m_axi.wvalid;
assign m_axi_wdata = m_axi.wdata;
assign m_axi_wstrb = m_axi.wstrb;
assign m_axi_bready = m_axi.bready;
assign m_axi.bvalid = m_axi_bvalid;
assign m_axi.bresp = m_axi_bresp;
assign m_axi.bid = 6'b0;
//Block memory
localparam BRAM_ADDR_W = $clog2(WORDS);
tdp_ram #(
.ADDR_WIDTH(BRAM_ADDR_W),
.NUM_COL(4),
.COL_WIDTH(8),
.PIPELINE_DEPTH(0),
.CASCADE_DEPTH(8),
.USE_PRELOAD(1),
.PRELOAD_FILE(LOCAL_MEM)
) local_mem (
.a_en(instruction_bram.en),
.a_wbe(instruction_bram.be),
.a_wdata(instruction_bram.data_in),
.a_addr(instruction_bram.addr[BRAM_ADDR_W-1:0]),
.a_rdata(instruction_bram.data_out),
.b_en(data_bram.en),
.b_wbe(data_bram.be),
.b_wdata(data_bram.data_in),
.b_addr(data_bram.addr[BRAM_ADDR_W-1:0]),
.b_rdata(data_bram.data_out),
.*);
endmodule

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puts "This script will create a system project for CVA5 in the current folder to run a demo application from block memory on the Nexys A7-100T"
puts "You should install the board support files from https://github.com/Digilent/vivado-boards before running this script"
# Create the project
create_project -force -part xc7a100tcsg324-1 CVA5BD ./vivado/CVA5BD
set_property board_part digilentinc.com:nexys-a7-100t:part0:1.3 [current_project]
set_property ip_repo_paths ./vivado/ip_repo [current_project]
update_ip_catalog
# Block diagram
create_bd_design "soc"
# UART
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0
apply_board_connection -board_interface "usb_uart" -ip_intf "axi_uartlite_0/UART" -diagram "soc"
# Reset
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0
apply_board_connection -board_interface "reset" -ip_intf "proc_sys_reset_0/ext_reset" -diagram "soc"
# Clock
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
# Connect to clock on board
apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {sys_clock ( System Clock ) } Manual_Source {Auto}} [get_bd_pins clk_wiz_0/clk_in1]
# Connect to reset on board via inverter
apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {reset ( Reset ) } Manual_Source {New External Port (ACTIVE_HIGH)}} [get_bd_pins clk_wiz_0/reset]
# Processor
create_bd_cell -type ip -vlnv xilinx.com:user:cva5_top:1.0 cva5_top_0
# Connect processor to UART via interconnect
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {Auto} Clk_slave {Auto} Clk_xbar {Auto} Master {/cva5_top_0/m_axi} Slave {/axi_uartlite_0/S_AXI} ddr_seg {Auto} intc_ip {New AXI Interconnect} master_apm {0}} [get_bd_intf_pins axi_uartlite_0/S_AXI]
# Set address space
set_property offset 0x60000000 [get_bd_addr_segs {cva5_top_0/m_axi/SEG_axi_uartlite_0_Reg}]
regenerate_bd_layout
make_wrapper -files [get_files ./vivado/CVA5BD/CVA5BD.srcs/sources_1/bd/soc/soc.bd] -top
add_files ./vivado/CVA5BD/CVA5BD.gen/sources_1/bd/soc/hdl/soc_wrapper.v
update_compile_order -fileset sources_1

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puts "This script will create a project for CVA5 in the current folder and package it as an IP"
# Create the project
create_project -force -part xc7a100tcsg324-1 CVA5IP ./vivado/CVA5IP
add_files -force {core examples/xilinx examples/sw}
set_property top cva5_top [current_fileset]
update_compile_order -fileset sources_1
# Now package as IP using intermediate project
ipx::package_project -root_dir ./vivado/ip_repo -vendor xilinx.com -library user -taxonomy /UserIP -import_files -set_current false -force
ipx::unload_core ./vivado/ip_repo/component.xml
ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory ./vivado/ip_repo ./vivado/ip_repo/component.xml
ipx::update_source_project_archive -component [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::check_integrity [ipx::current_core]
ipx::save_core [ipx::current_core]
ipx::move_temp_component_back -component [ipx::current_core]
close_project -delete
close_project

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Creating a Hardware Project for the Zedboard
-----------
We have provided a TCL script that automates the creation of a CVA5 system on a zedBoard through Vivado.
We also provide the manual steps that the script automate.
Hardware setup scripts and steps found here: [Hardware Setup](https://gitlab.com/sfu-rcl/taiga-project/-/wikis/Hardware-Setup)
Simulation setup scripts and steps found here: [Simulation Setup](https://gitlab.com/sfu-rcl/taiga-project/-/wikis/Simulation-Setup)

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/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
import cva5_config::*;
import cva5_types::*;
import l2_config_and_types::*;
module cva5_wrapper (
input logic sys_clk,
input logic ext_reset,
inout [14:0]DDR_addr,
inout [2:0]DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0]DDR_dm,
inout [31:0]DDR_dq,
inout [3:0]DDR_dqs_n,
inout [3:0]DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0]FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
input logic sin,
output logic sout
);
parameter SCRATCH_MEM_KB = 16;
parameter MEM_LINES = (SCRATCH_MEM_KB*1024)/4;
logic clk;
logic rst;
logic resetn;
axi_interface m_axi();
avalon_interface m_avalon();
wishbone_interface dwishbone();
wishbone_interface iwishbone();
l2_requester_interface l2[L2_NUM_PORTS-1:0]();
l2_memory_interface mem();
logic interrupt;
assign interrupt = 0;
//mem axi
logic [31:0]mem_axi_araddr;
logic [1:0]mem_axi_arburst;
logic [3:0]mem_axi_arcache;
logic [5:0]mem_axi_arid;
logic [7:0]mem_axi_arlen;
logic [0:0]mem_axi_arlock;
logic [2:0]mem_axi_arprot;
logic [3:0]mem_axi_arqos;
logic mem_axi_arready;
logic [3:0]mem_axi_arregion;
logic [2:0]mem_axi_arsize;
logic mem_axi_arvalid;
logic [31:0]mem_axi_awaddr;
logic [1:0]mem_axi_awburst;
logic [3:0]mem_axi_awcache;
logic [5:0]mem_axi_awid;
logic [7:0]mem_axi_awlen;
logic [0:0]mem_axi_awlock;
logic [2:0]mem_axi_awprot;
logic [3:0]mem_axi_awqos;
logic mem_axi_awready;
logic [3:0]mem_axi_awregion;
logic [2:0]mem_axi_awsize;
logic mem_axi_awvalid;
logic [5:0]mem_axi_bid;
logic mem_axi_bready;
logic [1:0]mem_axi_bresp;
logic mem_axi_bvalid;
logic [31:0]mem_axi_rdata;
logic [5:0]mem_axi_rid;
logic mem_axi_rlast;
logic mem_axi_rready;
logic [1:0]mem_axi_rresp;
logic mem_axi_rvalid;
logic [31:0]mem_axi_wdata;
logic mem_axi_wlast;
logic mem_axi_wready;
logic [3:0]mem_axi_wstrb;
logic mem_axi_wvalid;
logic [5:0] mem_axi_wid;
logic ACLK;
logic [31:0]bus_axi_araddr;
logic bus_axi_arready;
logic bus_axi_arvalid;
logic [31:0]bus_axi_awaddr;
logic bus_axi_awready;
logic bus_axi_awvalid;
logic bus_axi_bready;
logic [1:0]bus_axi_bresp;
logic bus_axi_bvalid;
logic [31:0]bus_axi_rdata;
logic bus_axi_rready;
logic [1:0]bus_axi_rresp;
logic bus_axi_rvalid;
logic [31:0]bus_axi_wdata;
logic bus_axi_wready;
logic [3:0]bus_axi_wstrb;
logic bus_axi_wvalid;
logic processor_reset;
//Arbiter AXI interface
logic axi_arready;
logic axi_arvalid;
logic[31:0] axi_araddr;
logic[3:0] axi_arlen;
logic[2:0] axi_arsize;
logic[1:0] axi_arburst;
logic[2:0] axi_arprot;
logic[3:0] axi_arcache;
logic[3:0] axi_arid;
logic [1:0]axi_arlock;
logic [3:0]axi_arqos;
//read data channel
logic axi_rready;
logic axi_rvalid;
logic[31:0] axi_rdata;
logic[1:0] axi_rresp;
logic axi_rlast;
logic[3:0] axi_rid;
//write addr channel
logic axi_awready;
logic axi_awvalid;
logic [31:0] axi_awaddr;
logic [7:0] axi_awlen;
logic [2:0] axi_awsize;
logic [1:0] axi_awburst;
logic [1:0]axi_awlock;
logic [3:0]axi_awqos;
logic [5:0]axi_awid;
logic[3:0] axi_awcache;
logic[2:0] axi_awprot;
//write data
logic axi_wready;
logic axi_wvalid;
logic [31:0] axi_wdata;
logic [3:0] axi_wstrb;
logic axi_wlast;
logic [5:0]axi_wid;
//write response
logic axi_bready;
logic axi_bvalid;
logic [1:0] axi_bresp;
logic [5:0]axi_bid;
logic axi_clk;
logic processor_clk;
assign axi_clk = clk;
assign rst = processor_reset;
assign m_axi.arready = bus_axi_arready;
assign bus_axi_arvalid = m_axi.arvalid;
assign bus_axi_araddr = m_axi.araddr[12:0];
//read data
assign bus_axi_rready = m_axi.rready;
assign m_axi.rvalid = bus_axi_rvalid;
assign m_axi.rdata = bus_axi_rdata;
assign m_axi.rresp = bus_axi_rresp;
//Write channel
//write address
assign m_axi.awready = bus_axi_awready;
assign bus_axi_awaddr = m_axi.awaddr[12:0];
assign bus_axi_awvalid = m_axi.awvalid;
//write data
assign m_axi.wready = bus_axi_wready;
assign bus_axi_wvalid = m_axi. wvalid;
assign bus_axi_wdata = m_axi.wdata;
assign bus_axi_wstrb = m_axi.wstrb;
//write response
assign bus_axi_bready = m_axi.bready;
assign m_axi.bvalid = bus_axi_bvalid;
assign m_axi.bresp = bus_axi_bresp;
local_memory_interface instruction_bram();
local_memory_interface data_bram();
cva5 cpu(.*, .l2(l2[0]));
//design_2 infra(.*);
generate
if (EXAMPLE_CONFIG.MODES == MSU || EXAMPLE_CONFIG.INCLUDE_ICACHE || EXAMPLE_CONFIG.INCLUDE_DCACHE) begin
l2_arbiter l2_arb (.*, .request(l2));
axi_to_arb l2_to_mem (.*, .l2(mem));
end
endgenerate
//arm proc(.*);
byte_en_bram #(MEM_LINES, "/home/ematthew/Research/RISCV/software2/riscv-tools/riscv-tests/benchmarks/fft.riscv.hw_init", 1) inst_data_ram (
.clk(clk),
.addr_a(instruction_bram.addr[$clog2(MEM_LINES)- 1:0]),
.en_a(instruction_bram.en),
.be_a(instruction_bram.be),
.data_in_a(instruction_bram.data_in),
.data_out_a(instruction_bram.data_out),
.addr_b(data_bram.addr[$clog2(MEM_LINES)- 1:0]),
.en_b(data_bram.en),
.be_b(data_bram.be),
.data_in_b(data_bram.data_in),
.data_out_b(data_bram.data_out)
);
endmodule

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examples/zedboard/dhrystone.riscv.hw_init
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examples/zedboard/dhrystone.riscv.sim_init
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examples/zedboard/scripts/cva5-ip-core-base.tcl
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examples/zedboard/scripts/design_1_wrapper.v
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@ -1,24 +0,0 @@
//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.2.1 (lin64) Build 2729669 Thu Dec 5 04:48:12 MST 2019
//Date : Fri Jul 24 11:12:29 2020
//Host : BefuddledZipper-Desktop.hitronhub.home running 64-bit unknown
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(sin,
sout);
input sin;
output sout;
wire sin;
wire sout;
design_1 design_1_i
(.sin(sin),
.sout(sout));
endmodule

374
examples/zedboard/scripts/zedboard_master_XDC_RevC_D_v3.xdc
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# ----------------------------------------------------------------------------
# _____
# / # /____ \____
# / \===\ \==/
# /___\===\___\/ AVNET Design Resource Center
# \======/ www.em.avnet.com/drc
# \====/
# ----------------------------------------------------------------------------
#
# Created With Avnet UCF Generator V0.4.0
# Date: Saturday, June 30, 2012
# Time: 12:18:55 AM
#
# This design is the property of Avnet. Publication of this
# design is not authorized without written consent from Avnet.
#
# Please direct any questions to:
# ZedBoard.org Community Forums
# http://www.zedboard.org
#
# Disclaimer:
# Avnet, Inc. makes no warranty for the use of this code or design.
# This code is provided "As Is". Avnet, Inc assumes no responsibility for
# any errors, which may appear in this code, nor does it make a commitment
# to update the information contained herein. Avnet, Inc specifically
# disclaims any implied warranties of fitness for a particular purpose.
# Copyright(c) 2012 Avnet, Inc.
# All rights reserved.
#
# ----------------------------------------------------------------------------
#
# Notes:
#
# 10 August 2012
# IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V,
# 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings.
# By default, Vadj is expected to be set to 1.8V but if a different
# voltage is used for a particular design, then the corresponding IO
# standard within this UCF should also be updated to reflect the actual
# Vadj jumper selection.
#
# 09 September 2012
# Net names are not allowed to contain hyphen characters '-' since this
# is not a legal VHDL87 or Verilog character within an identifier.
# HDL net names are adjusted to contain no hyphen characters '-' but
# rather use underscore '_' characters. Comment net name with the hyphen
# characters will remain in place since these are intended to match the
# schematic net names in order to better enable schematic search.
#
# 17 April 2014
# Pin constraint for toggle switch SW7 was corrected to M15 location.
#
# 16 April 2015
# Corrected the way that entire banks are assigned to a particular IO
# standard so that it works with more recent versions of Vivado Design
# Suite and moved the IO standard constraints to the end of the file
# along with some better organization and notes like we do with our SOMs.
#
# 6 June 2016
# Corrected error in signal name for package pin N19 (FMC Expansion Connector)
#
#
# ----------------------------------------------------------------------------
# ----------------------------------------------------------------------------
# Audio Codec - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}]; # "AC-ADR0"
#set_property PACKAGE_PIN Y5 [get_ports {AC_ADR1}]; # "AC-ADR1"
#set_property PACKAGE_PIN Y8 [get_ports {SDATA_O}]; # "AC-GPIO0"
#set_property PACKAGE_PIN AA7 [get_ports {SDATA_I}]; # "AC-GPIO1"
#set_property PACKAGE_PIN AA6 [get_ports {BCLK_O}]; # "AC-GPIO2"
#set_property PACKAGE_PIN Y6 [get_ports {LRCLK_O}]; # "AC-GPIO3"
#set_property PACKAGE_PIN AB2 [get_ports {MCLK_O}]; # "AC-MCLK"
#set_property PACKAGE_PIN AB4 [get_ports {iic_rtl_scl_io}]; # "AC-SCK"
#set_property PACKAGE_PIN AB5 [get_ports {iic_rtl_sda_io}]; # "AC-SDA"
# ----------------------------------------------------------------------------
# Clock Source - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN Y9 [get_ports axi_clk]
# ----------------------------------------------------------------------------
# JA Pmod - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN Y11 [get_ports {JA1}]; # "JA1"
#set_property PACKAGE_PIN AA8 [get_ports {JA10}]; # "JA10"
#set_property PACKAGE_PIN AA11 [get_ports {JA2}]; # "JA2"
set_property PACKAGE_PIN Y10 [get_ports sin]
set_property PACKAGE_PIN AA9 [get_ports sout]
#set_property PACKAGE_PIN AB11 [get_ports {JA7}]; # "JA7"
#set_property PACKAGE_PIN AB10 [get_ports {JA8}]; # "JA8"
#set_property PACKAGE_PIN AB9 [get_ports {JA9}]; # "JA9"
# ----------------------------------------------------------------------------
# JB Pmod - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN W12 [get_ports {JB1}]; # "JB1"
#set_property PACKAGE_PIN W11 [get_ports {JB2}]; # "JB2"
#set_property PACKAGE_PIN V10 [get_ports {JB3}]; # "JB3"
#set_property PACKAGE_PIN W8 [get_ports {JB4}]; # "JB4"
#set_property PACKAGE_PIN V12 [get_ports {JB7}]; # "JB7"
#set_property PACKAGE_PIN W10 [get_ports {JB8}]; # "JB8"
#set_property PACKAGE_PIN V9 [get_ports {JB9}]; # "JB9"
#set_property PACKAGE_PIN V8 [get_ports {JB10}]; # "JB10"
# ----------------------------------------------------------------------------
# JC Pmod - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN AB6 [get_ports {JC1_N}]; # "JC1_N"
#set_property PACKAGE_PIN AB7 [get_ports {JC1_P}]; # "JC1_P"
#set_property PACKAGE_PIN AA4 [get_ports {JC2_N}]; # "JC2_N"
#set_property PACKAGE_PIN Y4 [get_ports {JC2_P}]; # "JC2_P"
#set_property PACKAGE_PIN T6 [get_ports {JC3_N}]; # "JC3_N"
#set_property PACKAGE_PIN R6 [get_ports {JC3_P}]; # "JC3_P"
#set_property PACKAGE_PIN U4 [get_ports {JC4_N}]; # "JC4_N"
#set_property PACKAGE_PIN T4 [get_ports {JC4_P}]; # "JC4_P"
# ----------------------------------------------------------------------------
# JD Pmod - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN W7 [get_ports {JD1_N}]; # "JD1_N"
#set_property PACKAGE_PIN V7 [get_ports {JD1_P}]; # "JD1_P"
#set_property PACKAGE_PIN V4 [get_ports {JD2_N}]; # "JD2_N"
#set_property PACKAGE_PIN V5 [get_ports {JD2_P}]; # "JD2_P"
#set_property PACKAGE_PIN W5 [get_ports {JD3_N}]; # "JD3_N"
#set_property PACKAGE_PIN W6 [get_ports {JD3_P}]; # "JD3_P"
#set_property PACKAGE_PIN U5 [get_ports {JD4_N}]; # "JD4_N"
#set_property PACKAGE_PIN U6 [get_ports {JD4_P}]; # "JD4_P"
# ----------------------------------------------------------------------------
# OLED Display - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN U10 [get_ports {OLED_DC}]; # "OLED-DC"
#set_property PACKAGE_PIN U9 [get_ports {OLED_RES}]; # "OLED-RES"
#set_property PACKAGE_PIN AB12 [get_ports {OLED_SCLK}]; # "OLED-SCLK"
#set_property PACKAGE_PIN AA12 [get_ports {OLED_SDIN}]; # "OLED-SDIN"
#set_property PACKAGE_PIN U11 [get_ports {OLED_VBAT}]; # "OLED-VBAT"
#set_property PACKAGE_PIN U12 [get_ports {OLED_VDD}]; # "OLED-VDD"
# ----------------------------------------------------------------------------
# HDMI Output - Bank 33
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN W18 [get_ports {HD_CLK}]; # "HD-CLK"
#set_property PACKAGE_PIN Y13 [get_ports {HD_D0}]; # "HD-D0"
#set_property PACKAGE_PIN AA13 [get_ports {HD_D1}]; # "HD-D1"
#set_property PACKAGE_PIN W13 [get_ports {HD_D10}]; # "HD-D10"
#set_property PACKAGE_PIN W15 [get_ports {HD_D11}]; # "HD-D11"
#set_property PACKAGE_PIN V15 [get_ports {HD_D12}]; # "HD-D12"
#set_property PACKAGE_PIN U17 [get_ports {HD_D13}]; # "HD-D13"
#set_property PACKAGE_PIN V14 [get_ports {HD_D14}]; # "HD-D14"
#set_property PACKAGE_PIN V13 [get_ports {HS_D15}]; # "HD-D15"
#set_property PACKAGE_PIN AA14 [get_ports {HD_D2}]; # "HD-D2"
#set_property PACKAGE_PIN Y14 [get_ports {HD_D3}]; # "HD-D3"
#set_property PACKAGE_PIN AB15 [get_ports {HD_D4}]; # "HD-D4"
#set_property PACKAGE_PIN AB16 [get_ports {HD_D5}]; # "HD-D5"
#set_property PACKAGE_PIN AA16 [get_ports {HD_D6}]; # "HD-D6"
#set_property PACKAGE_PIN AB17 [get_ports {HD_D7}]; # "HD-D7"
#set_property PACKAGE_PIN AA17 [get_ports {HD_D8}]; # "HD-D8"
#set_property PACKAGE_PIN Y15 [get_ports {HD_D9}]; # "HD-D9"
#set_property PACKAGE_PIN U16 [get_ports {HD_DE}]; # "HD-DE"
#set_property PACKAGE_PIN V17 [get_ports {HD_HSYNC}]; # "HD-HSYNC"
#set_property PACKAGE_PIN W16 [get_ports {HD_INT}]; # "HD-INT"
#set_property PACKAGE_PIN AA18 [get_ports {HD_SCL}]; # "HD-SCL"
#set_property PACKAGE_PIN Y16 [get_ports {HD_SDA}]; # "HD-SDA"
#set_property PACKAGE_PIN U15 [get_ports {HD_SPDIF}]; # "HD-SPDIF"
#set_property PACKAGE_PIN Y18 [get_ports {HD_SPDIFO}]; # "HD-SPDIFO"
#set_property PACKAGE_PIN W17 [get_ports {HD_VSYNC}]; # "HD-VSYNC"
# ----------------------------------------------------------------------------
# User LEDs - Bank 33
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN T22 [get_ports {LD0}]; # "LD0"
#set_property PACKAGE_PIN T21 [get_ports {LD1}]; # "LD1"
#set_property PACKAGE_PIN U22 [get_ports {LD2}]; # "LD2"
#set_property PACKAGE_PIN U21 [get_ports {LD3}]; # "LD3"
#set_property PACKAGE_PIN V22 [get_ports {LD4}]; # "LD4"
#set_property PACKAGE_PIN W22 [get_ports {LD5}]; # "LD5"
#set_property PACKAGE_PIN U19 [get_ports {LD6}]; # "LD6"
#set_property PACKAGE_PIN U14 [get_ports {LD7}]; # "LD7"
# ----------------------------------------------------------------------------
# VGA Output - Bank 33
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN Y21 [get_ports {VGA_B1}]; # "VGA-B1"
#set_property PACKAGE_PIN Y20 [get_ports {VGA_B2}]; # "VGA-B2"
#set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}]; # "VGA-B3"
#set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}]; # "VGA-B4"
#set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}]; # "VGA-G1"
#set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}]; # "VGA-G2"
#set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}]; # "VGA-G3"
#set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}]; # "VGA-G4"
#set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}]; # "VGA-HS"
#set_property PACKAGE_PIN V20 [get_ports {VGA_R1}]; # "VGA-R1"
#set_property PACKAGE_PIN U20 [get_ports {VGA_R2}]; # "VGA-R2"
#set_property PACKAGE_PIN V19 [get_ports {VGA_R3}]; # "VGA-R3"
#set_property PACKAGE_PIN V18 [get_ports {VGA_R4}]; # "VGA-R4"
#set_property PACKAGE_PIN Y19 [get_ports {VGA_VS}]; # "VGA-VS"
# ----------------------------------------------------------------------------
# User Push Buttons - Bank 34
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN P16 [get_ports resetn]
#set_property PACKAGE_PIN R16 [get_ports {BTND}]; # "BTND"
#set_property PACKAGE_PIN N15 [get_ports {BTNL}]; # "BTNL"
#set_property PACKAGE_PIN R18 [get_ports {BTNR}]; # "BTNR"
#set_property PACKAGE_PIN T18 [get_ports {BTNU}]; # "BTNU"
# ----------------------------------------------------------------------------
# USB OTG Reset - Bank 34
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN L16 [get_ports {OTG_VBUSOC}]; # "OTG-VBUSOC"
# ----------------------------------------------------------------------------
# XADC GIO - Bank 34
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN H15 [get_ports {XADC_GIO0}]; # "XADC-GIO0"
#set_property PACKAGE_PIN R15 [get_ports {XADC_GIO1}]; # "XADC-GIO1"
#set_property PACKAGE_PIN K15 [get_ports {XADC_GIO2}]; # "XADC-GIO2"
#set_property PACKAGE_PIN J15 [get_ports {XADC_GIO3}]; # "XADC-GIO3"
# ----------------------------------------------------------------------------
# Miscellaneous - Bank 34
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN K16 [get_ports {PUDC_B}]; # "PUDC_B"
## ----------------------------------------------------------------------------
## USB OTG Reset - Bank 35
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN G17 [get_ports {OTG_RESETN}]; # "OTG-RESETN"
## ----------------------------------------------------------------------------
## User DIP Switches - Bank 35
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN F22 [get_ports {SW0}]; # "SW0"
#set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1"
#set_property PACKAGE_PIN H22 [get_ports {SW2}]; # "SW2"
#set_property PACKAGE_PIN F21 [get_ports {SW3}]; # "SW3"
#set_property PACKAGE_PIN H19 [get_ports {SW4}]; # "SW4"
#set_property PACKAGE_PIN H18 [get_ports {SW5}]; # "SW5"
#set_property PACKAGE_PIN H17 [get_ports {SW6}]; # "SW6"
#set_property PACKAGE_PIN M15 [get_ports {SW7}]; # "SW7"
## ----------------------------------------------------------------------------
## XADC AD Channels - Bank 35
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN E16 [get_ports {AD0N_R}]; # "XADC-AD0N-R"
#set_property PACKAGE_PIN F16 [get_ports {AD0P_R}]; # "XADC-AD0P-R"
#set_property PACKAGE_PIN D17 [get_ports {AD8N_N}]; # "XADC-AD8N-R"
#set_property PACKAGE_PIN D16 [get_ports {AD8P_R}]; # "XADC-AD8P-R"
## ----------------------------------------------------------------------------
## FMC Expansion Connector - Bank 13
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN R7 [get_ports {FMC_SCL}]; # "FMC-SCL"
#set_property PACKAGE_PIN U7 [get_ports {FMC_SDA}]; # "FMC-SDA"
## ----------------------------------------------------------------------------
## FMC Expansion Connector - Bank 33
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN AB14 [get_ports {FMC_PRSNT}]; # "FMC-PRSNT"
## ----------------------------------------------------------------------------
## FMC Expansion Connector - Bank 34
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN L19 [get_ports {FMC_CLK0_N}]; # "FMC-CLK0_N"
#set_property PACKAGE_PIN L18 [get_ports {FMC_CLK0_P}]; # "FMC-CLK0_P"
#set_property PACKAGE_PIN M20 [get_ports {FMC_LA00_CC_N}]; # "FMC-LA00_CC_N"
#set_property PACKAGE_PIN M19 [get_ports {FMC_LA00_CC_P}]; # "FMC-LA00_CC_P"
#set_property PACKAGE_PIN N20 [get_ports {FMC_LA01_CC_N}]; # "FMC-LA01_CC_N"
#set_property PACKAGE_PIN N19 [get_ports {FMC_LA01_CC_P}]; # "FMC-LA01_CC_P" - corrected 6/6/16 GE
#set_property PACKAGE_PIN P18 [get_ports {FMC_LA02_N}]; # "FMC-LA02_N"
#set_property PACKAGE_PIN P17 [get_ports {FMC_LA02_P}]; # "FMC-LA02_P"
#set_property PACKAGE_PIN P22 [get_ports {FMC_LA03_N}]; # "FMC-LA03_N"
#set_property PACKAGE_PIN N22 [get_ports {FMC_LA03_P}]; # "FMC-LA03_P"
#set_property PACKAGE_PIN M22 [get_ports {FMC_LA04_N}]; # "FMC-LA04_N"
#set_property PACKAGE_PIN M21 [get_ports {FMC_LA04_P}]; # "FMC-LA04_P"
#set_property PACKAGE_PIN K18 [get_ports {FMC_LA05_N}]; # "FMC-LA05_N"
#set_property PACKAGE_PIN J18 [get_ports {FMC_LA05_P}]; # "FMC-LA05_P"
#set_property PACKAGE_PIN L22 [get_ports {FMC_LA06_N}]; # "FMC-LA06_N"
#set_property PACKAGE_PIN L21 [get_ports {FMC_LA06_P}]; # "FMC-LA06_P"
#set_property PACKAGE_PIN T17 [get_ports {FMC_LA07_N}]; # "FMC-LA07_N"
#set_property PACKAGE_PIN T16 [get_ports {FMC_LA07_P}]; # "FMC-LA07_P"
#set_property PACKAGE_PIN J22 [get_ports {FMC_LA08_N}]; # "FMC-LA08_N"
#set_property PACKAGE_PIN J21 [get_ports {FMC_LA08_P}]; # "FMC-LA08_P"
#set_property PACKAGE_PIN R21 [get_ports {FMC_LA09_N}]; # "FMC-LA09_N"
#set_property PACKAGE_PIN R20 [get_ports {FMC_LA09_P}]; # "FMC-LA09_P"
#set_property PACKAGE_PIN T19 [get_ports {FMC_LA10_N}]; # "FMC-LA10_N"
#set_property PACKAGE_PIN R19 [get_ports {FMC_LA10_P}]; # "FMC-LA10_P"
#set_property PACKAGE_PIN N18 [get_ports {FMC_LA11_N}]; # "FMC-LA11_N"
#set_property PACKAGE_PIN N17 [get_ports {FMC_LA11_P}]; # "FMC-LA11_P"
#set_property PACKAGE_PIN P21 [get_ports {FMC_LA12_N}]; # "FMC-LA12_N"
#set_property PACKAGE_PIN P20 [get_ports {FMC_LA12_P}]; # "FMC-LA12_P"
#set_property PACKAGE_PIN M17 [get_ports {FMC_LA13_N}]; # "FMC-LA13_N"
#set_property PACKAGE_PIN L17 [get_ports {FMC_LA13_P}]; # "FMC-LA13_P"
#set_property PACKAGE_PIN K20 [get_ports {FMC_LA14_N}]; # "FMC-LA14_N"
#set_property PACKAGE_PIN K19 [get_ports {FMC_LA14_P}]; # "FMC-LA14_P"
#set_property PACKAGE_PIN J17 [get_ports {FMC_LA15_N}]; # "FMC-LA15_N"
#set_property PACKAGE_PIN J16 [get_ports {FMC_LA15_P}]; # "FMC-LA15_P"
#set_property PACKAGE_PIN K21 [get_ports {FMC_LA16_N}]; # "FMC-LA16_N"
#set_property PACKAGE_PIN J20 [get_ports {FMC_LA16_P}]; # "FMC-LA16_P"
## ----------------------------------------------------------------------------
## FMC Expansion Connector - Bank 35
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN C19 [get_ports {FMC_CLK1_N}]; # "FMC-CLK1_N"
#set_property PACKAGE_PIN D18 [get_ports {FMC_CLK1_P}]; # "FMC-CLK1_P"
#set_property PACKAGE_PIN B20 [get_ports {FMC_LA17_CC_N}]; # "FMC-LA17_CC_N"
#set_property PACKAGE_PIN B19 [get_ports {FMC_LA17_CC_P}]; # "FMC-LA17_CC_P"
#set_property PACKAGE_PIN C20 [get_ports {FMC_LA18_CC_N}]; # "FMC-LA18_CC_N"
#set_property PACKAGE_PIN D20 [get_ports {FMC_LA18_CC_P}]; # "FMC-LA18_CC_P"
#set_property PACKAGE_PIN G16 [get_ports {FMC_LA19_N}]; # "FMC-LA19_N"
#set_property PACKAGE_PIN G15 [get_ports {FMC_LA19_P}]; # "FMC-LA19_P"
#set_property PACKAGE_PIN G21 [get_ports {FMC_LA20_N}]; # "FMC-LA20_N"
#set_property PACKAGE_PIN G20 [get_ports {FMC_LA20_P}]; # "FMC-LA20_P"
#set_property PACKAGE_PIN E20 [get_ports {FMC_LA21_N}]; # "FMC-LA21_N"
#set_property PACKAGE_PIN E19 [get_ports {FMC_LA21_P}]; # "FMC-LA21_P"
#set_property PACKAGE_PIN F19 [get_ports {FMC_LA22_N}]; # "FMC-LA22_N"
#set_property PACKAGE_PIN G19 [get_ports {FMC_LA22_P}]; # "FMC-LA22_P"
#set_property PACKAGE_PIN D15 [get_ports {FMC_LA23_N}]; # "FMC-LA23_N"
#set_property PACKAGE_PIN E15 [get_ports {FMC_LA23_P}]; # "FMC-LA23_P"
#set_property PACKAGE_PIN A19 [get_ports {FMC_LA24_N}]; # "FMC-LA24_N"
#set_property PACKAGE_PIN A18 [get_ports {FMC_LA24_P}]; # "FMC-LA24_P"
#set_property PACKAGE_PIN C22 [get_ports {FMC_LA25_N}]; # "FMC-LA25_N"
#set_property PACKAGE_PIN D22 [get_ports {FMC_LA25_P}]; # "FMC-LA25_P"
#set_property PACKAGE_PIN E18 [get_ports {FMC_LA26_N}]; # "FMC-LA26_N"
#set_property PACKAGE_PIN F18 [get_ports {FMC_LA26_P}]; # "FMC-LA26_P"
#set_property PACKAGE_PIN D21 [get_ports {FMC_LA27_N}]; # "FMC-LA27_N"
#set_property PACKAGE_PIN E21 [get_ports {FMC_LA27_P}]; # "FMC-LA27_P"
#set_property PACKAGE_PIN A17 [get_ports {FMC_LA28_N}]; # "FMC-LA28_N"
#set_property PACKAGE_PIN A16 [get_ports {FMC_LA28_P}]; # "FMC-LA28_P"
#set_property PACKAGE_PIN C18 [get_ports {FMC_LA29_N}]; # "FMC-LA29_N"
#set_property PACKAGE_PIN C17 [get_ports {FMC_LA29_P}]; # "FMC-LA29_P"
#set_property PACKAGE_PIN B15 [get_ports {FMC_LA30_N}]; # "FMC-LA30_N"
#set_property PACKAGE_PIN C15 [get_ports {FMC_LA30_P}]; # "FMC-LA30_P"
#set_property PACKAGE_PIN B17 [get_ports {FMC_LA31_N}]; # "FMC-LA31_N"
#set_property PACKAGE_PIN B16 [get_ports {FMC_LA31_P}]; # "FMC-LA31_P"
#set_property PACKAGE_PIN A22 [get_ports {FMC_LA32_N}]; # "FMC-LA32_N"
#set_property PACKAGE_PIN A21 [get_ports {FMC_LA32_P}]; # "FMC-LA32_P"
#set_property PACKAGE_PIN B22 [get_ports {FMC_LA33_N}]; # "FMC-LA33_N"
#set_property PACKAGE_PIN B21 [get_ports {FMC_LA33_P}]; # "FMC-LA33_P"
# ----------------------------------------------------------------------------
# IOSTANDARD Constraints
#
# Note that these IOSTANDARD constraints are applied to all IOs currently
# assigned within an I/O bank. If these IOSTANDARD constraints are
# evaluated prior to other PACKAGE_PIN constraints being applied, then
# the IOSTANDARD specified will likely not be applied properly to those
# pins. Therefore, bank wide IOSTANDARD constraints should be placed
# within the XDC file in a location that is evaluated AFTER all
# PACKAGE_PIN constraints within the target bank have been evaluated.
#
# Un-comment one or more of the following IOSTANDARD constraints according to
# the bank pin assignments that are required within a design.
# ----------------------------------------------------------------------------
# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard.
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
# Set the bank voltage for IO Bank 34 to 1.8V by default.
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 34]];
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]]
# Set the bank voltage for IO Bank 35 to 1.8V by default.
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 35]];
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]

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examples/zedboard/system_periperhals.tcl
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################################################################
# This is a generated script based on design: design_2
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2017.3
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source design_2_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xc7z020clg484-1
set_property BOARD_PART em.avnet.com:zed:part0:0.9 [current_project]
}
# CHANGE DESIGN NAME HERE
set design_name design_2
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 axi ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {200000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {6} \
CONFIG.MAX_BURST_LENGTH {16} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {8} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI3} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $axi
set bus_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 bus_axi ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {13} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {200000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {1} \
CONFIG.NUM_READ_OUTSTANDING {1} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {1} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4LITE} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $bus_axi
set mem_axi [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 mem_axi ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {200000000} \
CONFIG.PROTOCOL {AXI4} \
] $mem_axi
# Create ports
set axi_clk [ create_bd_port -dir I -type clk axi_clk ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {bus_axi:axi:mem_axi} \
CONFIG.FREQ_HZ {200000000} \
] $axi_clk
set processor_clk [ create_bd_port -dir O processor_clk ]
set processor_reset [ create_bd_port -dir O processor_reset ]
set resetn [ create_bd_port -dir I -type rst resetn ]
set sin [ create_bd_port -dir I sin ]
set sout [ create_bd_port -dir O sout ]
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
] $axi_interconnect_0
# Create instance: axi_uart16550_0, and set properties
set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ]
set_property -dict [ list \
CONFIG.C_EXTERNAL_XIN_CLK_HZ {25000000} \
CONFIG.C_S_AXI_ACLK_FREQ_HZ {200000000} \
] $axi_uart16550_0
# Need to retain value_src of defaults
set_property -dict [ list \
CONFIG.C_EXTERNAL_XIN_CLK_HZ.VALUE_SRC {DEFAULT} \
] $axi_uart16550_0
# Create instance: microblaze_0_axi_periph, and set properties
set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
] $microblaze_0_axi_periph
# Create instance: rst_clk_wiz_1_100M, and set properties
set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ]
# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports bus_axi] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net S00_AXI_2 [get_bd_intf_ports axi] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports mem_axi] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uart16550_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]
# Create port connections
connect_bd_net -net axi_uart16550_0_sout [get_bd_ports sout] [get_bd_pins axi_uart16550_0/sout]
connect_bd_net -net microblaze_0_Clk [get_bd_ports axi_clk] [get_bd_ports processor_clk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk]
connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]
connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn]
connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_ports processor_reset] [get_bd_pins rst_clk_wiz_1_100M/mb_reset]
connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn]
connect_bd_net -net sin_1 [get_bd_ports sin] [get_bd_pins axi_uart16550_0/sin]
# Create address segments
create_bd_addr_seg -range 0x10000000 -offset 0x80000000 [get_bd_addr_spaces axi] [get_bd_addr_segs mem_axi/Reg] SEG_M00_AXI_Reg
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces bus_axi] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] SEG_axi_uart16550_0_Reg
# Perform GUI Layout
regenerate_bd_layout -layout_string {
guistr: "# # String gsaved with Nlview 6.6.5b 2016-09-06 bk=1.3687 VDI=39 GEI=35 GUI=JA:1.6
# -string -flagsOSRD
preplace port bus_axi -pg 1 -y 30 -defaultsOSRD
preplace port processor_clk -pg 1 -y 500 -defaultsOSRD
preplace port sin -pg 1 -y 440 -defaultsOSRD
preplace port resetn -pg 1 -y 100 -defaultsOSRD
preplace port axi -pg 1 -y 250 -defaultsOSRD
preplace port sout -pg 1 -y 280 -defaultsOSRD
preplace port processor_reset -pg 1 -y 460 -defaultsOSRD
preplace port axi_clk -pg 1 -y 170 -defaultsOSRD
preplace port mem_axi -pg 1 -y 310 -defaultsOSRD
preplace inst microblaze_0_axi_periph -pg 1 -lvl 3 -y 90 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 1 -y 310 -defaultsOSRD
preplace inst rst_clk_wiz_1_100M -pg 1 -lvl 2 -y 80 -defaultsOSRD
preplace inst axi_uart16550_0 -pg 1 -lvl 2 -y 270 -defaultsOSRD
preplace netloc sin_1 1 0 3 NJ 440 NJ 440 1060
preplace netloc microblaze_0_Clk 1 0 4 -40 -30 340J -30 1090 -30 1410
preplace netloc axi_uart16550_0_sout 1 2 2 N 280 NJ
preplace netloc microblaze_0_axi_periph_M00_AXI 1 1 3 350 -70 NJ -70 1400
preplace netloc resetn_1 1 0 2 -30J 60 N
preplace netloc rst_clk_wiz_1_100M_interconnect_aresetn 1 2 1 1080
preplace netloc S00_AXI_1 1 0 3 -50J -10 NJ -10 1070J
preplace netloc rst_clk_wiz_1_100M_peripheral_aresetn 1 0 3 -30 430 350 430 1100
preplace netloc rst_clk_wiz_1_100M_mb_reset 1 2 2 1070 460 NJ
preplace netloc axi_interconnect_0_M00_AXI 1 1 3 340J 350 NJ 350 1420J
preplace netloc S00_AXI_2 1 0 1 N
levelinfo -pg 1 -70 200 890 1260 1450 -top -110 -bot 1110
",
}
# Restore current instance
current_bd_instance $oldCurInst
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""

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# ----------------------------------------------------------------------------
# _____
# / # /____ \____
# / \===\ \==/
# /___\===\___\/ AVNET Design Resource Center
# \======/ www.em.avnet.com/drc
# \====/
# ----------------------------------------------------------------------------
#
# Created With Avnet UCF Generator V0.4.0
# Date: Saturday, June 30, 2012
# Time: 12:18:55 AM
#
# This design is the property of Avnet. Publication of this
# design is not authorized without written consent from Avnet.
#
# Please direct any questions to:
# ZedBoard.org Community Forums
# http://www.zedboard.org
#
# Disclaimer:
# Avnet, Inc. makes no warranty for the use of this code or design.
# This code is provided "As Is". Avnet, Inc assumes no responsibility for
# any errors, which may appear in this code, nor does it make a commitment
# to update the information contained herein. Avnet, Inc specifically
# disclaims any implied warranties of fitness for a particular purpose.
# Copyright(c) 2012 Avnet, Inc.
# All rights reserved.
#
# ----------------------------------------------------------------------------
#
# Notes:
#
# 10 August 2012
# IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V,
# 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings.
# By default, Vadj is expected to be set to 1.8V but if a different
# voltage is used for a particular design, then the corresponding IO
# standard within this UCF should also be updated to reflect the actual
# Vadj jumper selection.
#
# 09 September 2012
# Net names are not allowed to contain hyphen characters '-' since this
# is not a legal VHDL87 or Verilog character within an identifier.
# HDL net names are adjusted to contain no hyphen characters '-' but
# rather use underscore '_' characters. Comment net name with the hyphen
# characters will remain in place since these are intended to match the
# schematic net names in order to better enable schematic search.
#
# 17 April 2014
# Pin constraint for toggle switch SW7 was corrected to M15 location.
#
# 16 April 2015
# Corrected the way that entire banks are assigned to a particular IO
# standard so that it works with more recent versions of Vivado Design
# Suite and moved the IO standard constraints to the end of the file
# along with some better organization and notes like we do with our SOMs.
#
# 6 June 2016
# Corrected error in signal name for package pin N19 (FMC Expansion Connector)
#
#
# ----------------------------------------------------------------------------
# ----------------------------------------------------------------------------
# Audio Codec - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}]; # "AC-ADR0"
#set_property PACKAGE_PIN Y5 [get_ports {AC_ADR1}]; # "AC-ADR1"
#set_property PACKAGE_PIN Y8 [get_ports {SDATA_O}]; # "AC-GPIO0"
#set_property PACKAGE_PIN AA7 [get_ports {SDATA_I}]; # "AC-GPIO1"
#set_property PACKAGE_PIN AA6 [get_ports {BCLK_O}]; # "AC-GPIO2"
#set_property PACKAGE_PIN Y6 [get_ports {LRCLK_O}]; # "AC-GPIO3"
#set_property PACKAGE_PIN AB2 [get_ports {MCLK_O}]; # "AC-MCLK"
#set_property PACKAGE_PIN AB4 [get_ports {iic_rtl_scl_io}]; # "AC-SCK"
#set_property PACKAGE_PIN AB5 [get_ports {iic_rtl_sda_io}]; # "AC-SDA"
# ----------------------------------------------------------------------------
# Clock Source - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN Y9 [get_ports axi_clk]
# ----------------------------------------------------------------------------
# JA Pmod - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN Y11 [get_ports {JA1}]; # "JA1"
#set_property PACKAGE_PIN AA8 [get_ports {JA10}]; # "JA10"
#set_property PACKAGE_PIN AA11 [get_ports {JA2}]; # "JA2"
set_property PACKAGE_PIN Y10 [get_ports sin]
set_property PACKAGE_PIN AA9 [get_ports sout]
#set_property PACKAGE_PIN AB11 [get_ports {JA7}]; # "JA7"
#set_property PACKAGE_PIN AB10 [get_ports {JA8}]; # "JA8"
#set_property PACKAGE_PIN AB9 [get_ports {JA9}]; # "JA9"
# ----------------------------------------------------------------------------
# JB Pmod - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN W12 [get_ports {JB1}]; # "JB1"
#set_property PACKAGE_PIN W11 [get_ports {JB2}]; # "JB2"
#set_property PACKAGE_PIN V10 [get_ports {JB3}]; # "JB3"
#set_property PACKAGE_PIN W8 [get_ports {JB4}]; # "JB4"
#set_property PACKAGE_PIN V12 [get_ports {JB7}]; # "JB7"
#set_property PACKAGE_PIN W10 [get_ports {JB8}]; # "JB8"
#set_property PACKAGE_PIN V9 [get_ports {JB9}]; # "JB9"
#set_property PACKAGE_PIN V8 [get_ports {JB10}]; # "JB10"
# ----------------------------------------------------------------------------
# JC Pmod - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN AB6 [get_ports {JC1_N}]; # "JC1_N"
#set_property PACKAGE_PIN AB7 [get_ports {JC1_P}]; # "JC1_P"
#set_property PACKAGE_PIN AA4 [get_ports {JC2_N}]; # "JC2_N"
#set_property PACKAGE_PIN Y4 [get_ports {JC2_P}]; # "JC2_P"
#set_property PACKAGE_PIN T6 [get_ports {JC3_N}]; # "JC3_N"
#set_property PACKAGE_PIN R6 [get_ports {JC3_P}]; # "JC3_P"
#set_property PACKAGE_PIN U4 [get_ports {JC4_N}]; # "JC4_N"
#set_property PACKAGE_PIN T4 [get_ports {JC4_P}]; # "JC4_P"
# ----------------------------------------------------------------------------
# JD Pmod - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN W7 [get_ports {JD1_N}]; # "JD1_N"
#set_property PACKAGE_PIN V7 [get_ports {JD1_P}]; # "JD1_P"
#set_property PACKAGE_PIN V4 [get_ports {JD2_N}]; # "JD2_N"
#set_property PACKAGE_PIN V5 [get_ports {JD2_P}]; # "JD2_P"
#set_property PACKAGE_PIN W5 [get_ports {JD3_N}]; # "JD3_N"
#set_property PACKAGE_PIN W6 [get_ports {JD3_P}]; # "JD3_P"
#set_property PACKAGE_PIN U5 [get_ports {JD4_N}]; # "JD4_N"
#set_property PACKAGE_PIN U6 [get_ports {JD4_P}]; # "JD4_P"
# ----------------------------------------------------------------------------
# OLED Display - Bank 13
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN U10 [get_ports {OLED_DC}]; # "OLED-DC"
#set_property PACKAGE_PIN U9 [get_ports {OLED_RES}]; # "OLED-RES"
#set_property PACKAGE_PIN AB12 [get_ports {OLED_SCLK}]; # "OLED-SCLK"
#set_property PACKAGE_PIN AA12 [get_ports {OLED_SDIN}]; # "OLED-SDIN"
#set_property PACKAGE_PIN U11 [get_ports {OLED_VBAT}]; # "OLED-VBAT"
#set_property PACKAGE_PIN U12 [get_ports {OLED_VDD}]; # "OLED-VDD"
# ----------------------------------------------------------------------------
# HDMI Output - Bank 33
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN W18 [get_ports {HD_CLK}]; # "HD-CLK"
#set_property PACKAGE_PIN Y13 [get_ports {HD_D0}]; # "HD-D0"
#set_property PACKAGE_PIN AA13 [get_ports {HD_D1}]; # "HD-D1"
#set_property PACKAGE_PIN W13 [get_ports {HD_D10}]; # "HD-D10"
#set_property PACKAGE_PIN W15 [get_ports {HD_D11}]; # "HD-D11"
#set_property PACKAGE_PIN V15 [get_ports {HD_D12}]; # "HD-D12"
#set_property PACKAGE_PIN U17 [get_ports {HD_D13}]; # "HD-D13"
#set_property PACKAGE_PIN V14 [get_ports {HD_D14}]; # "HD-D14"
#set_property PACKAGE_PIN V13 [get_ports {HS_D15}]; # "HD-D15"
#set_property PACKAGE_PIN AA14 [get_ports {HD_D2}]; # "HD-D2"
#set_property PACKAGE_PIN Y14 [get_ports {HD_D3}]; # "HD-D3"
#set_property PACKAGE_PIN AB15 [get_ports {HD_D4}]; # "HD-D4"
#set_property PACKAGE_PIN AB16 [get_ports {HD_D5}]; # "HD-D5"
#set_property PACKAGE_PIN AA16 [get_ports {HD_D6}]; # "HD-D6"
#set_property PACKAGE_PIN AB17 [get_ports {HD_D7}]; # "HD-D7"
#set_property PACKAGE_PIN AA17 [get_ports {HD_D8}]; # "HD-D8"
#set_property PACKAGE_PIN Y15 [get_ports {HD_D9}]; # "HD-D9"
#set_property PACKAGE_PIN U16 [get_ports {HD_DE}]; # "HD-DE"
#set_property PACKAGE_PIN V17 [get_ports {HD_HSYNC}]; # "HD-HSYNC"
#set_property PACKAGE_PIN W16 [get_ports {HD_INT}]; # "HD-INT"
#set_property PACKAGE_PIN AA18 [get_ports {HD_SCL}]; # "HD-SCL"
#set_property PACKAGE_PIN Y16 [get_ports {HD_SDA}]; # "HD-SDA"
#set_property PACKAGE_PIN U15 [get_ports {HD_SPDIF}]; # "HD-SPDIF"
#set_property PACKAGE_PIN Y18 [get_ports {HD_SPDIFO}]; # "HD-SPDIFO"
#set_property PACKAGE_PIN W17 [get_ports {HD_VSYNC}]; # "HD-VSYNC"
# ----------------------------------------------------------------------------
# User LEDs - Bank 33
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN T22 [get_ports {LD0}]; # "LD0"
#set_property PACKAGE_PIN T21 [get_ports {LD1}]; # "LD1"
#set_property PACKAGE_PIN U22 [get_ports {LD2}]; # "LD2"
#set_property PACKAGE_PIN U21 [get_ports {LD3}]; # "LD3"
#set_property PACKAGE_PIN V22 [get_ports {LD4}]; # "LD4"
#set_property PACKAGE_PIN W22 [get_ports {LD5}]; # "LD5"
#set_property PACKAGE_PIN U19 [get_ports {LD6}]; # "LD6"
#set_property PACKAGE_PIN U14 [get_ports {LD7}]; # "LD7"
# ----------------------------------------------------------------------------
# VGA Output - Bank 33
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN Y21 [get_ports {VGA_B1}]; # "VGA-B1"
#set_property PACKAGE_PIN Y20 [get_ports {VGA_B2}]; # "VGA-B2"
#set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}]; # "VGA-B3"
#set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}]; # "VGA-B4"
#set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}]; # "VGA-G1"
#set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}]; # "VGA-G2"
#set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}]; # "VGA-G3"
#set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}]; # "VGA-G4"
#set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}]; # "VGA-HS"
#set_property PACKAGE_PIN V20 [get_ports {VGA_R1}]; # "VGA-R1"
#set_property PACKAGE_PIN U20 [get_ports {VGA_R2}]; # "VGA-R2"
#set_property PACKAGE_PIN V19 [get_ports {VGA_R3}]; # "VGA-R3"
#set_property PACKAGE_PIN V18 [get_ports {VGA_R4}]; # "VGA-R4"
#set_property PACKAGE_PIN Y19 [get_ports {VGA_VS}]; # "VGA-VS"
# ----------------------------------------------------------------------------
# User Push Buttons - Bank 34
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN P16 [get_ports resetn]
#set_property PACKAGE_PIN R16 [get_ports {BTND}]; # "BTND"
#set_property PACKAGE_PIN N15 [get_ports {BTNL}]; # "BTNL"
#set_property PACKAGE_PIN R18 [get_ports {BTNR}]; # "BTNR"
#set_property PACKAGE_PIN T18 [get_ports {BTNU}]; # "BTNU"
# ----------------------------------------------------------------------------
# USB OTG Reset - Bank 34
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN L16 [get_ports {OTG_VBUSOC}]; # "OTG-VBUSOC"
# ----------------------------------------------------------------------------
# XADC GIO - Bank 34
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN H15 [get_ports {XADC_GIO0}]; # "XADC-GIO0"
#set_property PACKAGE_PIN R15 [get_ports {XADC_GIO1}]; # "XADC-GIO1"
#set_property PACKAGE_PIN K15 [get_ports {XADC_GIO2}]; # "XADC-GIO2"
#set_property PACKAGE_PIN J15 [get_ports {XADC_GIO3}]; # "XADC-GIO3"
# ----------------------------------------------------------------------------
# Miscellaneous - Bank 34
# ----------------------------------------------------------------------------
#set_property PACKAGE_PIN K16 [get_ports {PUDC_B}]; # "PUDC_B"
## ----------------------------------------------------------------------------
## USB OTG Reset - Bank 35
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN G17 [get_ports {OTG_RESETN}]; # "OTG-RESETN"
## ----------------------------------------------------------------------------
## User DIP Switches - Bank 35
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN F22 [get_ports {SW0}]; # "SW0"
#set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1"
#set_property PACKAGE_PIN H22 [get_ports {SW2}]; # "SW2"
#set_property PACKAGE_PIN F21 [get_ports {SW3}]; # "SW3"
#set_property PACKAGE_PIN H19 [get_ports {SW4}]; # "SW4"
#set_property PACKAGE_PIN H18 [get_ports {SW5}]; # "SW5"
#set_property PACKAGE_PIN H17 [get_ports {SW6}]; # "SW6"
#set_property PACKAGE_PIN M15 [get_ports {SW7}]; # "SW7"
## ----------------------------------------------------------------------------
## XADC AD Channels - Bank 35
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN E16 [get_ports {AD0N_R}]; # "XADC-AD0N-R"
#set_property PACKAGE_PIN F16 [get_ports {AD0P_R}]; # "XADC-AD0P-R"
#set_property PACKAGE_PIN D17 [get_ports {AD8N_N}]; # "XADC-AD8N-R"
#set_property PACKAGE_PIN D16 [get_ports {AD8P_R}]; # "XADC-AD8P-R"
## ----------------------------------------------------------------------------
## FMC Expansion Connector - Bank 13
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN R7 [get_ports {FMC_SCL}]; # "FMC-SCL"
#set_property PACKAGE_PIN U7 [get_ports {FMC_SDA}]; # "FMC-SDA"
## ----------------------------------------------------------------------------
## FMC Expansion Connector - Bank 33
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN AB14 [get_ports {FMC_PRSNT}]; # "FMC-PRSNT"
## ----------------------------------------------------------------------------
## FMC Expansion Connector - Bank 34
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN L19 [get_ports {FMC_CLK0_N}]; # "FMC-CLK0_N"
#set_property PACKAGE_PIN L18 [get_ports {FMC_CLK0_P}]; # "FMC-CLK0_P"
#set_property PACKAGE_PIN M20 [get_ports {FMC_LA00_CC_N}]; # "FMC-LA00_CC_N"
#set_property PACKAGE_PIN M19 [get_ports {FMC_LA00_CC_P}]; # "FMC-LA00_CC_P"
#set_property PACKAGE_PIN N20 [get_ports {FMC_LA01_CC_N}]; # "FMC-LA01_CC_N"
#set_property PACKAGE_PIN N19 [get_ports {FMC_LA01_CC_P}]; # "FMC-LA01_CC_P" - corrected 6/6/16 GE
#set_property PACKAGE_PIN P18 [get_ports {FMC_LA02_N}]; # "FMC-LA02_N"
#set_property PACKAGE_PIN P17 [get_ports {FMC_LA02_P}]; # "FMC-LA02_P"
#set_property PACKAGE_PIN P22 [get_ports {FMC_LA03_N}]; # "FMC-LA03_N"
#set_property PACKAGE_PIN N22 [get_ports {FMC_LA03_P}]; # "FMC-LA03_P"
#set_property PACKAGE_PIN M22 [get_ports {FMC_LA04_N}]; # "FMC-LA04_N"
#set_property PACKAGE_PIN M21 [get_ports {FMC_LA04_P}]; # "FMC-LA04_P"
#set_property PACKAGE_PIN K18 [get_ports {FMC_LA05_N}]; # "FMC-LA05_N"
#set_property PACKAGE_PIN J18 [get_ports {FMC_LA05_P}]; # "FMC-LA05_P"
#set_property PACKAGE_PIN L22 [get_ports {FMC_LA06_N}]; # "FMC-LA06_N"
#set_property PACKAGE_PIN L21 [get_ports {FMC_LA06_P}]; # "FMC-LA06_P"
#set_property PACKAGE_PIN T17 [get_ports {FMC_LA07_N}]; # "FMC-LA07_N"
#set_property PACKAGE_PIN T16 [get_ports {FMC_LA07_P}]; # "FMC-LA07_P"
#set_property PACKAGE_PIN J22 [get_ports {FMC_LA08_N}]; # "FMC-LA08_N"
#set_property PACKAGE_PIN J21 [get_ports {FMC_LA08_P}]; # "FMC-LA08_P"
#set_property PACKAGE_PIN R21 [get_ports {FMC_LA09_N}]; # "FMC-LA09_N"
#set_property PACKAGE_PIN R20 [get_ports {FMC_LA09_P}]; # "FMC-LA09_P"
#set_property PACKAGE_PIN T19 [get_ports {FMC_LA10_N}]; # "FMC-LA10_N"
#set_property PACKAGE_PIN R19 [get_ports {FMC_LA10_P}]; # "FMC-LA10_P"
#set_property PACKAGE_PIN N18 [get_ports {FMC_LA11_N}]; # "FMC-LA11_N"
#set_property PACKAGE_PIN N17 [get_ports {FMC_LA11_P}]; # "FMC-LA11_P"
#set_property PACKAGE_PIN P21 [get_ports {FMC_LA12_N}]; # "FMC-LA12_N"
#set_property PACKAGE_PIN P20 [get_ports {FMC_LA12_P}]; # "FMC-LA12_P"
#set_property PACKAGE_PIN M17 [get_ports {FMC_LA13_N}]; # "FMC-LA13_N"
#set_property PACKAGE_PIN L17 [get_ports {FMC_LA13_P}]; # "FMC-LA13_P"
#set_property PACKAGE_PIN K20 [get_ports {FMC_LA14_N}]; # "FMC-LA14_N"
#set_property PACKAGE_PIN K19 [get_ports {FMC_LA14_P}]; # "FMC-LA14_P"
#set_property PACKAGE_PIN J17 [get_ports {FMC_LA15_N}]; # "FMC-LA15_N"
#set_property PACKAGE_PIN J16 [get_ports {FMC_LA15_P}]; # "FMC-LA15_P"
#set_property PACKAGE_PIN K21 [get_ports {FMC_LA16_N}]; # "FMC-LA16_N"
#set_property PACKAGE_PIN J20 [get_ports {FMC_LA16_P}]; # "FMC-LA16_P"
## ----------------------------------------------------------------------------
## FMC Expansion Connector - Bank 35
## ----------------------------------------------------------------------------
#set_property PACKAGE_PIN C19 [get_ports {FMC_CLK1_N}]; # "FMC-CLK1_N"
#set_property PACKAGE_PIN D18 [get_ports {FMC_CLK1_P}]; # "FMC-CLK1_P"
#set_property PACKAGE_PIN B20 [get_ports {FMC_LA17_CC_N}]; # "FMC-LA17_CC_N"
#set_property PACKAGE_PIN B19 [get_ports {FMC_LA17_CC_P}]; # "FMC-LA17_CC_P"
#set_property PACKAGE_PIN C20 [get_ports {FMC_LA18_CC_N}]; # "FMC-LA18_CC_N"
#set_property PACKAGE_PIN D20 [get_ports {FMC_LA18_CC_P}]; # "FMC-LA18_CC_P"
#set_property PACKAGE_PIN G16 [get_ports {FMC_LA19_N}]; # "FMC-LA19_N"
#set_property PACKAGE_PIN G15 [get_ports {FMC_LA19_P}]; # "FMC-LA19_P"
#set_property PACKAGE_PIN G21 [get_ports {FMC_LA20_N}]; # "FMC-LA20_N"
#set_property PACKAGE_PIN G20 [get_ports {FMC_LA20_P}]; # "FMC-LA20_P"
#set_property PACKAGE_PIN E20 [get_ports {FMC_LA21_N}]; # "FMC-LA21_N"
#set_property PACKAGE_PIN E19 [get_ports {FMC_LA21_P}]; # "FMC-LA21_P"
#set_property PACKAGE_PIN F19 [get_ports {FMC_LA22_N}]; # "FMC-LA22_N"
#set_property PACKAGE_PIN G19 [get_ports {FMC_LA22_P}]; # "FMC-LA22_P"
#set_property PACKAGE_PIN D15 [get_ports {FMC_LA23_N}]; # "FMC-LA23_N"
#set_property PACKAGE_PIN E15 [get_ports {FMC_LA23_P}]; # "FMC-LA23_P"
#set_property PACKAGE_PIN A19 [get_ports {FMC_LA24_N}]; # "FMC-LA24_N"
#set_property PACKAGE_PIN A18 [get_ports {FMC_LA24_P}]; # "FMC-LA24_P"
#set_property PACKAGE_PIN C22 [get_ports {FMC_LA25_N}]; # "FMC-LA25_N"
#set_property PACKAGE_PIN D22 [get_ports {FMC_LA25_P}]; # "FMC-LA25_P"
#set_property PACKAGE_PIN E18 [get_ports {FMC_LA26_N}]; # "FMC-LA26_N"
#set_property PACKAGE_PIN F18 [get_ports {FMC_LA26_P}]; # "FMC-LA26_P"
#set_property PACKAGE_PIN D21 [get_ports {FMC_LA27_N}]; # "FMC-LA27_N"
#set_property PACKAGE_PIN E21 [get_ports {FMC_LA27_P}]; # "FMC-LA27_P"
#set_property PACKAGE_PIN A17 [get_ports {FMC_LA28_N}]; # "FMC-LA28_N"
#set_property PACKAGE_PIN A16 [get_ports {FMC_LA28_P}]; # "FMC-LA28_P"
#set_property PACKAGE_PIN C18 [get_ports {FMC_LA29_N}]; # "FMC-LA29_N"
#set_property PACKAGE_PIN C17 [get_ports {FMC_LA29_P}]; # "FMC-LA29_P"
#set_property PACKAGE_PIN B15 [get_ports {FMC_LA30_N}]; # "FMC-LA30_N"
#set_property PACKAGE_PIN C15 [get_ports {FMC_LA30_P}]; # "FMC-LA30_P"
#set_property PACKAGE_PIN B17 [get_ports {FMC_LA31_N}]; # "FMC-LA31_N"
#set_property PACKAGE_PIN B16 [get_ports {FMC_LA31_P}]; # "FMC-LA31_P"
#set_property PACKAGE_PIN A22 [get_ports {FMC_LA32_N}]; # "FMC-LA32_N"
#set_property PACKAGE_PIN A21 [get_ports {FMC_LA32_P}]; # "FMC-LA32_P"
#set_property PACKAGE_PIN B22 [get_ports {FMC_LA33_N}]; # "FMC-LA33_N"
#set_property PACKAGE_PIN B21 [get_ports {FMC_LA33_P}]; # "FMC-LA33_P"
# ----------------------------------------------------------------------------
# IOSTANDARD Constraints
#
# Note that these IOSTANDARD constraints are applied to all IOs currently
# assigned within an I/O bank. If these IOSTANDARD constraints are
# evaluated prior to other PACKAGE_PIN constraints being applied, then
# the IOSTANDARD specified will likely not be applied properly to those
# pins. Therefore, bank wide IOSTANDARD constraints should be placed
# within the XDC file in a location that is evaluated AFTER all
# PACKAGE_PIN constraints within the target bank have been evaluated.
#
# Un-comment one or more of the following IOSTANDARD constraints according to
# the bank pin assignments that are required within a design.
# ----------------------------------------------------------------------------
# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard.
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
# Set the bank voltage for IO Bank 34 to 1.8V by default.
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 34]];
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]]
# Set the bank voltage for IO Bank 35 to 1.8V by default.
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 35]];
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]

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l2_arbiter/axi_to_arb.sv
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/*
* Copyright © 2017-2019 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module axi_to_arb
import cva5_config::*;
import riscv_types::*;
import cva5_types::*;
import l2_config_and_types::*;
(
input logic clk,
input logic rst,
//read addr channel
input logic axi_arready,
output logic axi_arvalid,
output logic[31:0] axi_araddr,
output logic[7:0] axi_arlen,
output logic[2:0] axi_arsize,
output logic[1:0] axi_arburst,
output logic[2:0] axi_arprot,
output logic[3:0] axi_arcache,
output logic[5:0] axi_arid,
//read data channel
output logic axi_rready,
input logic axi_rvalid,
input logic[31:0] axi_rdata,
input logic[1:0] axi_rresp,
input logic axi_rlast,
input logic[5:0] axi_rid,
//write addr channel
input logic axi_awready,
output logic axi_awvalid,
output logic [31:0] axi_awaddr,
output logic [7:0] axi_awlen,
output logic [2:0] axi_awsize,
output logic [1:0] axi_awburst,
output logic[3:0] axi_awcache,
output logic[2:0] axi_awprot,
//write data
input logic axi_wready,
output logic axi_wvalid,
output logic [31:0] axi_wdata,
output logic [3:0] axi_wstrb,
output logic axi_wlast,
//write response
output logic axi_bready,
input logic axi_bvalid,
input logic [1:0] axi_bresp,
//arb interface
l2_memory_interface.slave l2
);
logic pop_request;
logic read_modify_write;
logic read_modify_write_in_progress;
logic address_phase_complete;
logic [31:0] amo_result;
logic [31:0] amo_result_r;
logic [$clog2(EXAMPLE_CONFIG.DCACHE.LINE_W)-1:0] read_count;
logic amo_write_ready;
logic[4:0] write_reference_burst_count;
amo_alu_inputs_t amo_alu_inputs;
logic write_in_progress;
logic write_transfer_complete;
logic pop;
logic[4:0] write_burst_count;
logic[4:0] burst_count, burst_count_r;
logic on_last_burst;
//AMO read modify write support ****************************************************
assign read_modify_write = l2.is_amo && (l2.amo_type_or_burst_size != AMO_LR_FN5 || l2.amo_type_or_burst_size != AMO_SC_FN5);
always_ff @ (posedge clk) begin
if (rst)
read_modify_write_in_progress <= 0;
else if (axi_bvalid)
read_modify_write_in_progress <= 0;
else if (l2.request_valid & read_modify_write)
read_modify_write_in_progress <= 1;
end
always_ff @ (posedge clk) begin
if (rst)
address_phase_complete <= 0;
else if (pop)
address_phase_complete <= 0;
else if (axi_arvalid & axi_arready)
address_phase_complete <= 1;
end
//TODO: if the data cache is made non-blocking on a miss then we could capture a previous request here instead of the one we just issued
//safe under current circumstances as subsequent load won't be issued until the first one returns.
always_ff @ (posedge clk) begin
if (rst)
read_count <= 0;
else if (axi_rvalid && (axi_rid == 6'(l2.id)))
read_count <= read_count + 1;
end
assign amo_alu_inputs.rs1_load = axi_rdata;
assign amo_alu_inputs.rs2 = l2.wr_data;
assign amo_alu_inputs.op = l2.amo_type_or_burst_size;
amo_alu amo_unit (.*, .result(amo_result));
//TODO: assumption that all data caches have same line size, would have to update wrt the burst size to be safe if they have different line lengths
//also update araddr
always_ff @ (posedge clk) begin
if (axi_rvalid && (read_count == l2.addr[$clog2(EXAMPLE_CONFIG.DCACHE.LINE_W)-1:0]))
amo_result_r <= amo_result;
end
always_ff @ (posedge clk) begin
if (rst)
amo_write_ready <= 0;
else if (pop)
amo_write_ready <= 0;
else if (l2.is_amo && axi_rvalid && read_count == l2.addr[$clog2(EXAMPLE_CONFIG.DCACHE.LINE_W)-1:0])
amo_write_ready <= 1;
end
//End AMO
assign burst_count = l2.amo_type_or_burst_size;
//read constants
assign axi_arlen = 8'(burst_count); //
assign axi_arburst = 2'b01;// INCR
assign axi_rready = 1; //always ready to receive data
assign axi_arsize = 3'b010;//4 bytes
assign axi_arcache = 4'b0011; //bufferable cacheable memory
assign axi_arprot = '0;
assign axi_arid = 6'(l2.id);
assign axi_araddr ={l2.addr, 2'b00} & {25'h1FFFFFF, ~burst_count, 2'b00};
assign write_reference_burst_count = read_modify_write ? 0 : burst_count;
//write constants
assign axi_awlen = 8'(write_reference_burst_count);
assign axi_awburst = 2'b01;// INCR
assign axi_awsize = 3'b010;//4 bytes
assign axi_bready = 1;
assign axi_awcache = 4'b0011;//bufferable cacheable memory
assign axi_awprot = '0;
assign axi_awaddr ={l2.addr, 2'b00};
assign axi_wdata = read_modify_write ? amo_result_r : l2.wr_data;
assign axi_wstrb = read_modify_write ? '1 : l2.wr_data_be;
//Done when read request sent, or slave ack on write data
assign pop = (axi_arvalid & axi_arready & ~read_modify_write) | (on_last_burst & axi_wready);
assign l2.request_pop = pop;
//read channel
always_ff @ (posedge clk) begin
if (rst)
axi_arvalid <= 0;
else if (axi_arvalid & axi_arready)
axi_arvalid <= 0;
else if (l2.request_valid & l2.rnw & ~address_phase_complete)
axi_arvalid <= 1;
end
//write channel
logic write_request;
logic write_in_progress_r;
assign write_request = l2.wr_data_valid & l2.request_valid & (~l2.rnw | amo_write_ready);
assign axi_awvalid = write_request & ~write_in_progress_r;
always_ff @ (posedge clk) begin
if (rst)
write_in_progress_r <= 0;
else if (on_last_burst & axi_wready)
write_in_progress_r <= 0;
else if (axi_awready & write_request)
write_in_progress_r <= 1;
end
assign write_in_progress = write_in_progress_r | (axi_awready & write_request);
always_ff @ (posedge clk) begin
if (rst)
write_burst_count <= 0;
else if (on_last_burst & axi_wready)
write_burst_count <= 0;
else if (axi_wvalid & axi_wready)
write_burst_count <= write_burst_count+1;
end
assign on_last_burst = (write_in_progress && write_reference_burst_count == write_burst_count);
assign axi_wvalid = write_in_progress & l2.wr_data_valid;
assign axi_wlast = on_last_burst & l2.wr_data_valid;
assign l2.wr_data_read = write_in_progress & axi_wready;
//read response
assign l2.rd_data = axi_rdata;
assign l2.rd_id = axi_rid[L2_ID_W-1:0];
assign l2.rd_data_valid = axi_rvalid;
endmodule

312
l2_arbiter/l2_arbiter.sv
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@ -1,312 +0,0 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module l2_arbiter
import l2_config_and_types::*;
import riscv_types::*;
import cva5_types::*;
(
input logic clk,
input logic rst,
l2_requester_interface.slave request [L2_NUM_PORTS-1:0],
l2_memory_interface.master mem
);
l2_arbitration_interface arb();
//FIFO interfaces
fifo_interface #(.DATA_TYPE(l2_request_t)) input_fifos [L2_NUM_PORTS-1:0]();
fifo_interface #(.DATA_TYPE(l2_data_request_t)) input_data_fifos [L2_NUM_PORTS-1:0]();
fifo_interface #(.DATA_TYPE(logic[29:0])) inv_response_fifos [L2_NUM_PORTS-1:0]();
fifo_interface #(.DATA_TYPE(l2_return_data_t)) returndata_fifos [L2_NUM_PORTS-1:0]();
fifo_interface #(.DATA_TYPE(l2_mem_request_t)) mem_addr_fifo();
fifo_interface #(.DATA_TYPE(l2_data_request_t)) mem_data_fifo();
fifo_interface #(.DATA_TYPE(l2_data_attributes_t)) data_attributes();
fifo_interface #(.DATA_TYPE(l2_mem_return_data_t)) mem_returndata_fifo();
l2_mem_request_t mem_addr_fifo_data_out;
l2_request_t requests_in[L2_NUM_PORTS-1:0];
l2_data_request_t data_requests_in[L2_NUM_PORTS-1:0];
logic advance;
l2_request_t arb_request;
l2_mem_request_t mem_request;
logic reserv_valid;
logic reserv_lr;
logic reserv_sc;
logic reserv_store;
l2_request_t requests [L2_NUM_PORTS-1:0];
l2_request_t reserv_request;
logic [$clog2(L2_NUM_PORTS)-1:0] reserv_id;
logic [L2_NUM_PORTS-1:0] reserv_id_v;
logic write_done;
logic [4:0] burst_count;
l2_data_attributes_t new_attr;
l2_data_attributes_t current_attr;
l2_data_request_t input_data [L2_NUM_PORTS-1:0];
l2_mem_return_data_t mem_return_data;
l2_return_data_t return_data [L2_NUM_PORTS-1:0];
logic [L2_NUM_PORTS-1:0] return_push;
logic wr_clk, rd_clk;
assign wr_clk = clk;
assign rd_clk = clk;
//Implementation
//************************************
/*************************************
* Input Request FIFOs
*************************************/
genvar i;
generate for (i=0; i < L2_NUM_PORTS; i++) begin : gen_requests
//Requester FIFO side
assign input_fifos[i].push = request[i].request_push;
assign input_fifos[i].potential_push = request[i].request_push;
//Repack input attributes
assign requests_in[i].addr = request[i].addr;
assign requests_in[i].rnw = request[i].rnw;
assign requests_in[i].is_amo = request[i].is_amo;
assign requests_in[i].amo_type_or_burst_size = request[i].amo_type_or_burst_size;
assign requests_in[i].sub_id = request[i].sub_id;
assign input_fifos[i].data_in = requests_in[i];
assign input_fifos[i].pop = input_fifos[i].valid & arb.grantee_v[i] & ~mem_addr_fifo.full;
assign request[i].request_full = input_fifos[i].full;
//FIFO instantiation
cva5_fifo #(.DATA_TYPE(l2_request_t), .FIFO_DEPTH(L2_INPUT_FIFO_DEPTHS)) input_fifo (.*, .fifo(input_fifos[i]));
//Arbiter FIFO side
assign requests[i] = input_fifos[i].data_out;
assign arb.requests[i] = input_fifos[i].valid;
end
endgenerate
/*************************************
* Input Data FIFOs
*************************************/
generate for (i=0; i < L2_NUM_PORTS; i++) begin : gen_input_fifos
//Requester FIFO side
assign input_data_fifos[i].push = request[i].wr_data_push;
assign input_data_fifos[i].potential_push = request[i].wr_data_push;
assign data_requests_in[i].data = request[i].wr_data;
assign data_requests_in[i].be = request[i].wr_data_be;
assign input_data_fifos[i].data_in = data_requests_in[i];
assign request[i].data_full = input_data_fifos[i].full;
//FIFO instantiation
cva5_fifo #(.DATA_TYPE(l2_data_request_t), .FIFO_DEPTH(L2_INPUT_FIFO_DEPTHS)) input_data_fifo (.*, .fifo(input_data_fifos[i]));
//Arbiter FIFO side
assign input_data_fifos[i].pop = (data_attributes.valid && (current_attr.id == i) && ~mem_data_fifo.full);
assign input_data[i] = input_data_fifos[i].data_out;
end
endgenerate
/*************************************
* Arbitration
*************************************/
l2_round_robin rr (.*);
assign advance = arb.grantee_valid & ~mem_addr_fifo.full;
assign arb.strobe = advance;
assign mem_addr_fifo.push = advance;
assign mem_addr_fifo.potential_push = advance;
assign mem_addr_fifo.pop = mem.request_pop;
assign mem.request_valid = mem_addr_fifo.valid;
assign arb_request = requests[arb.grantee_i];
assign mem_request.addr = arb_request.addr;
assign mem_request.rnw = arb_request.rnw;
assign mem_request.is_amo = arb_request.is_amo;
assign mem_request.amo_type_or_burst_size = arb_request.amo_type_or_burst_size;
assign mem_request.id = {arb.grantee_i, arb_request.sub_id};
assign mem_addr_fifo.data_in = mem_request;
//unpack memory request attributes
assign mem_addr_fifo_data_out = mem_addr_fifo.data_out;
assign mem.addr = mem_addr_fifo_data_out.addr;
assign mem.rnw = mem_addr_fifo_data_out.rnw;
assign mem.is_amo = mem_addr_fifo_data_out.is_amo;
assign mem.amo_type_or_burst_size = mem_addr_fifo_data_out.amo_type_or_burst_size;
assign mem.id = mem_addr_fifo_data_out.id;
cva5_fifo #(.DATA_TYPE(l2_mem_request_t), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) input_fifo (.*, .fifo(mem_addr_fifo));
/*************************************
* Reservation Support
*************************************/
always_ff @(posedge clk) begin
if (advance) begin
reserv_request <= requests[arb.grantee_i];
reserv_id <= arb.grantee_i;
reserv_id_v <= arb.grantee_v;
end
end
always_ff @(posedge clk) begin
if (rst)
reserv_valid <= 0;
else
reserv_valid <= advance;
end
assign reserv_lr = (reserv_request.is_amo && reserv_request.amo_type_or_burst_size == AMO_LR_FN5);
assign reserv_sc = (reserv_request.is_amo && reserv_request.amo_type_or_burst_size == AMO_SC_FN5);
assign reserv_store = ~reserv_request.rnw | (reserv_request.is_amo && reserv_request.amo_type_or_burst_size != AMO_LR_FN5);
l2_reservation_logic reserv (.*,
.addr(reserv_request.addr),
.id(reserv_id),
.strobe(reserv_valid),
.lr (reserv_lr),
.sc (reserv_sc),
.store (reserv_store),
.abort_request(mem.abort_request)
);
//sc response
generate for (i=0; i < L2_NUM_PORTS; i++) begin : gen_sc_response
always_ff @(posedge clk) begin
if (rst) begin
request[i].con_result <= 0;
request[i].con_valid <= 0;
end
else begin
request[i].con_result <= ~mem.abort_request;
request[i].con_valid <= reserv_sc & reserv_valid & reserv_id_v[i];
end
end
end
endgenerate
//inv response
generate for (i=0; i < L2_NUM_PORTS; i++) begin : gen_inv_response
//Requester FIFO side
assign inv_response_fifos[i].pop = request[i].inv_ack;
assign request[i].inv_addr = inv_response_fifos[i].data_out;
assign request[i].inv_valid = inv_response_fifos[i].valid;
//FIFO instantiation
cva5_fifo #(.DATA_TYPE(logic[29:0]), .FIFO_DEPTH(L2_INVALIDATION_FIFO_DEPTHS)) inv_response_fifo (.*, .fifo(inv_response_fifos[i]));
//Arbiter side
assign inv_response_fifos[i].push = reserv_valid & reserv_store & ~reserv_id_v[i];
assign inv_response_fifos[i].potential_push = reserv_valid & reserv_store & ~reserv_id_v[i];
assign inv_response_fifos[i].data_in = reserv_request.addr;
end
endgenerate
/*************************************
* Data stage
*************************************/
assign new_attr.id = reserv_id;
assign new_attr.burst_size = reserv_request.amo_type_or_burst_size;
assign new_attr.abort_request = mem.abort_request;
assign data_attributes.data_in = new_attr;
assign data_attributes.push = reserv_valid & ~reserv_request.rnw & ~mem.abort_request;
assign data_attributes.potential_push = reserv_valid & ~reserv_request.rnw & ~mem.abort_request;
cva5_fifo #(.DATA_TYPE(l2_data_attributes_t), .FIFO_DEPTH(L2_DATA_ATTRIBUTES_FIFO_DEPTH)) data_attributes_fifo (.*, .fifo(data_attributes));
assign data_attributes.pop = write_done;
assign current_attr = data_attributes.data_out;
always_ff @(posedge clk) begin
if (rst)
burst_count <= 0;
else if (write_done)
burst_count <= 0;
else if (data_attributes.valid & ~mem_data_fifo.full)
burst_count <= burst_count + 1;
end
assign write_done = data_attributes.valid & ~mem_data_fifo.full & (burst_count == current_attr.burst_size);
cva5_fifo #(.DATA_TYPE(l2_data_request_t), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) mem_data (.*, .fifo(mem_data_fifo));
assign mem_data_fifo.push = data_attributes.valid & ~mem_data_fifo.full & ~current_attr.abort_request;
assign mem_data_fifo.potential_push = data_attributes.valid & ~mem_data_fifo.full & ~current_attr.abort_request;
assign mem_data_fifo.data_in = input_data[current_attr.id];
l2_data_request_t mem_data_request;
assign mem_data_request = mem_data_fifo.data_out;
assign mem.wr_data = mem_data_request.data;
assign mem.wr_data_be = mem_data_request.be;
assign mem.wr_data_valid = mem_data_fifo.valid;
assign mem_data_fifo.pop = mem.wr_data_read;
/*************************************
* Read response
*************************************/
cva5_fifo # (.DATA_TYPE(l2_mem_return_data_t), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) mem_returndata (.*, .fifo(mem_returndata_fifo));
assign mem_returndata_fifo.push = mem.rd_data_valid;
assign mem_returndata_fifo.potential_push = mem.rd_data_valid;
assign mem_returndata_fifo.data_in = {mem.rd_id, mem.rd_data};
assign mem_return_data = mem_returndata_fifo.data_out;
assign mem_returndata_fifo.pop = mem_returndata_fifo.valid;
always_comb begin
return_push = '0;
return_push[mem_return_data.id] = mem_returndata_fifo.valid;
end
generate for (i=0; i < L2_NUM_PORTS; i++) begin : gen_return_data
//Requester FIFO side
assign returndata_fifos[i].pop = request[i].rd_data_ack;
assign return_data[i] = returndata_fifos[i].data_out;
assign request[i].rd_data =return_data[i].data;
assign request[i].rd_sub_id = return_data[i].sub_id;
assign request[i].rd_data_valid = returndata_fifos[i].valid;
//FIFO instantiation
cva5_fifo #(.DATA_TYPE(l2_return_data_t), .FIFO_DEPTH(L2_READ_RETURN_FIFO_DEPTHS)) returndata_fifo (.*, .fifo(returndata_fifos[i]));
//Arbiter side
assign returndata_fifos[i].push = return_push[i];
assign returndata_fifos[i].potential_push = return_push[i];
assign returndata_fifos[i].data_in = {mem_return_data.sub_id, mem_return_data.data};
end
endgenerate
endmodule

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@ -1,92 +0,0 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
package l2_config_and_types;
localparam L2_NUM_PORTS = 2;
parameter L2_SUB_ID_W = 2; //Kept as parameter, due to localparam failing with scripted IP packaging
//localparam int L2_INPUT_FIFO_DEPTHS [7 : 0] = '{4, 4, 4, 4, 4, 4, 4, 4};
//localparam int L2_INVALIDATION_FIFO_DEPTHS [7 : 0] = '{4, 4, 4, 4, 4, 4, 4, 4};
//localparam int L2_READ_RETURN_FIFO_DEPTHS [7 : 0] = '{1, 1, 1, 1, 1, 1, 1, 1};//depth 1, rd_ack will be trimmed
localparam L2_INPUT_FIFO_DEPTHS = 16;
localparam L2_INVALIDATION_FIFO_DEPTHS = 16;
localparam L2_READ_RETURN_FIFO_DEPTHS = 1;//depth 1, rd_ack will be trimmed
localparam L2_MEM_ADDR_FIFO_DEPTH = 16;
localparam L2_DATA_ATTRIBUTES_FIFO_DEPTH = 32;//Sized larger to remove need to check full status
//Convenience derivative parameters
localparam L2_ID_W = $clog2(L2_NUM_PORTS) + L2_SUB_ID_W;
typedef struct packed{
logic [29:0] addr;
logic rnw;
logic is_amo;
logic [4:0] amo_type_or_burst_size;
logic [L2_SUB_ID_W-1:0] sub_id;
} l2_request_t;
typedef struct packed{
logic [31:0] data;
logic [3:0] be;
} l2_data_request_t;
typedef struct packed{
logic [29:0] addr;
logic [3:0] be;
logic rnw;
logic is_amo;
logic [4:0] amo_type_or_burst_size;
logic [L2_ID_W-1:0] id;
} l2_mem_request_t;
typedef struct packed{
logic [$clog2(L2_NUM_PORTS)-1:0] id;
logic [4:0] burst_size;
logic abort_request;
} l2_data_attributes_t;
typedef struct packed{
logic [$clog2(L2_NUM_PORTS)-1:0] id;
logic [L2_SUB_ID_W-1:0] sub_id;
logic [31:0] data;
} l2_mem_return_data_t;
typedef struct packed{
logic [L2_SUB_ID_W-1:0] sub_id;
logic [31:0] data;
} l2_return_data_t;
endpackage

105
l2_arbiter/l2_external_interfaces.sv
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@ -1,105 +0,0 @@
/*
* Copyright © 2019 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
interface l2_requester_interface;
import l2_config_and_types::*;
//l2_request_t request;
logic [29:0] addr;
logic rnw;
logic is_amo;
logic [4:0] amo_type_or_burst_size;
logic [L2_SUB_ID_W-1:0] sub_id;
logic request_push;
logic request_full;
logic [31:2] inv_addr;
logic inv_valid;
logic inv_ack;
logic con_result;
logic con_valid;
logic [31:0] wr_data;
logic [3:0] wr_data_be;
logic wr_data_push;
logic data_full;
logic [31:0] rd_data;
logic [L2_SUB_ID_W-1:0] rd_sub_id;
logic rd_data_valid;
logic rd_data_ack;
modport master (output addr, rnw, is_amo, amo_type_or_burst_size, sub_id,
output request_push, input request_full,
input inv_addr, inv_valid, output inv_ack,
input con_result, con_valid,
output wr_data, wr_data_be, wr_data_push, input data_full,
input rd_data, rd_sub_id, rd_data_valid, output rd_data_ack);
modport slave (input addr, rnw, is_amo, amo_type_or_burst_size, sub_id,
input request_push, output request_full,
output inv_addr, inv_valid, input inv_ack,
output con_result, con_valid,
input wr_data, wr_data_be, wr_data_push, output data_full,
output rd_data, rd_sub_id, rd_data_valid, input rd_data_ack);
endinterface
interface l2_memory_interface;
import l2_config_and_types::*;
localparam L2_ID_W = $clog2(L2_NUM_PORTS) + L2_SUB_ID_W;
logic [29:0] addr;
logic rnw;
logic is_amo;
logic [4:0] amo_type_or_burst_size;
logic [L2_ID_W-1:0] id;
logic request_pop;
logic request_valid;
logic abort_request;
logic [31:0] wr_data;
logic [3:0] wr_data_be;
logic wr_data_valid;
logic wr_data_read;
logic [31:0] rd_data;
logic [L2_ID_W-1:0] rd_id;
logic rd_data_valid;
modport master (output addr, rnw, is_amo, amo_type_or_burst_size, id,
output request_valid, abort_request, input request_pop,
output wr_data, wr_data_be, wr_data_valid, input wr_data_read,
input rd_data, rd_id, rd_data_valid);
modport slave (input addr, rnw, is_amo, amo_type_or_burst_size, id,
input request_valid, abort_request, output request_pop,
input wr_data, wr_data_be, wr_data_valid, output wr_data_read,
output rd_data, rd_id, rd_data_valid);
endinterface

103
l2_arbiter/l2_fifo.sv
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@ -1,103 +0,0 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module l2_fifo #(parameter DATA_WIDTH = 32, parameter FIFO_DEPTH = 4, parameter ASYNC = 0)
(
input logic clk,
input logic wr_clk,
input logic rd_clk,
input logic rst,
l2_fifo_interface.structure fifo
);
generate if (ASYNC) begin : gen_async
end
else
begin : gen_sync
if (FIFO_DEPTH == 1) begin
always_ff @ (posedge clk) begin
if (rst)
fifo.valid <= 0;
else if (fifo.push)
fifo.valid <= 1;
else
fifo.valid <= 0;
end
always_ff @ (posedge clk) begin
if (fifo.push)
fifo.data_out <= fifo.data_in;
end
end
else begin
logic[DATA_WIDTH-1:0] lut_ram[FIFO_DEPTH-1:0];
logic[$clog2(FIFO_DEPTH)-1:0] write_index;
logic[$clog2(FIFO_DEPTH)-1:0] read_index;
logic count_v [FIFO_DEPTH:0];
////////////////////////////////////////////////////////
//implementation
assign fifo.data_out = lut_ram[read_index];
always_ff @ (posedge clk) begin
if (rst) begin
read_index <= '0;
write_index <= '0;
end
else begin
read_index <= read_index + $clog2(FIFO_DEPTH)'(fifo.pop);
write_index <= write_index + $clog2(FIFO_DEPTH)'(fifo.push);
end
end
assign fifo.full = count_v[FIFO_DEPTH];
assign fifo.valid = ~count_v[0];
always_ff @ (posedge clk) begin
if (fifo.push)
lut_ram[write_index] <= fifo.data_in;
end
always_ff @ (posedge clk) begin
if (rst) begin
count_v[0] <= 1;
for (int i = 1; i <= FIFO_DEPTH; i++) count_v[i] <= 0;
end
else if (fifo.push & ~fifo.pop) begin
count_v[FIFO_DEPTH:1] <= count_v[FIFO_DEPTH-1:0];
count_v[0] <= 1'b0;
end else if (~fifo.push & fifo.pop) begin
count_v[FIFO_DEPTH] <= 1'b0;
count_v[FIFO_DEPTH-1:0] <= count_v[FIFO_DEPTH:1];
end
end
end
end
endgenerate
endmodule

35
l2_arbiter/l2_interfaces.sv
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@ -1,35 +0,0 @@
/*
* Copyright © 2017-2019 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
interface l2_arbitration_interface;
import l2_config_and_types::*;
logic [L2_NUM_PORTS-1:0] requests;
logic [$clog2(L2_NUM_PORTS)-1:0] grantee_i;
logic [L2_NUM_PORTS-1:0] grantee_v;
logic grantee_valid;
logic strobe;
modport slave (input requests, strobe, output grantee_i, grantee_v , grantee_valid);
modport master (output requests, strobe, input grantee_i, grantee_v , grantee_valid);
endinterface

80
l2_arbiter/l2_reservation_logic.sv
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@ -1,80 +0,0 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module l2_reservation_logic
import l2_config_and_types::*;
(
input logic clk,
input logic rst,
input logic [31:2] addr,
input logic [$clog2(L2_NUM_PORTS)-1:0] id,
input logic strobe,
input logic lr,
input logic sc,
input logic store, //includes read-modify-write AMOs
output logic abort_request
);
logic [31:2] reservation_address [L2_NUM_PORTS-1:0];
logic [L2_NUM_PORTS-1:0] reservation;
logic [L2_NUM_PORTS-1:0] address_match;
logic [L2_NUM_PORTS-1:0] revoke_reservation;
always_comb begin
for (int i = 0; i < L2_NUM_PORTS; i++) begin
address_match[i] = (reservation_address[i] == addr);
revoke_reservation[i] = sc | (store & address_match[i]);
end
end
always_ff @(posedge clk) begin
for (int i = 0; i < L2_NUM_PORTS; i++) begin
if (rst)
reservation[i] <= 0;
else if (strobe) begin
if (revoke_reservation[i])
reservation[i] <= 0;
else if (lr)
reservation[i] <= 1;
end
end
end
always_ff @(posedge clk) begin
if (strobe & lr)
reservation_address[id] <= addr;
end
assign abort_request = sc && (~reservation[id] || (reservation[id] && ~address_match[id]));
endmodule

74
l2_arbiter/l2_round_robin.sv
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@ -1,74 +0,0 @@
/*
* Copyright © 2017 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module l2_round_robin
import l2_config_and_types::*;
(
input logic clk,
input logic rst,
l2_arbitration_interface.slave arb
);
logic [$clog2(L2_NUM_PORTS)-1:0] state;
logic[$clog2(L2_NUM_PORTS)-1:0] muxes [L2_NUM_PORTS-1:0];
generate if(L2_NUM_PORTS == 1) begin : gen_width_one
assign arb.grantee_valid = arb.requests[0];
assign arb.grantee_v = arb.requests;
assign arb.grantee_i = 0;
end else begin : gen_width_2plus
//Lowest priority to current state
always_ff @(posedge clk) begin
if (rst)
state <= 0;
else if (arb.strobe)
state <= arb.grantee_i;
end
//ex: state 0, highest priority to L2_NUM_PORTS-1
always_comb begin
for (int i = 0; i < L2_NUM_PORTS; i++) begin
muxes[i] = $clog2(L2_NUM_PORTS)'(i);
for (int j = 0; j < L2_NUM_PORTS; j++) begin
if (arb.requests[(i + j) % L2_NUM_PORTS])
muxes[i] = $clog2(L2_NUM_PORTS)'((i + j) % L2_NUM_PORTS);
end
end
end
//Select mux output based on current state
assign arb.grantee_i = muxes[state];
//Integer to one-hot
assign arb.grantee_v = 1 << arb.grantee_i;
//any valid request
assign arb.grantee_valid = |arb.requests;
end
endgenerate
endmodule

54
local_memory/local_mem.sv
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@ -1,54 +0,0 @@
/*
* Copyright © 2018 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
module local_mem
#(
parameter RAM_SIZE = 64,
parameter preload_file = "",
parameter USE_PRELOAD_FILE = 0
)
(
input logic clk,
input logic rst,
local_memory_interface.slave portA,
local_memory_interface.slave portB
);
localparam LINES = (RAM_SIZE/4)*1024; //RAM width is 32-bits, so for RAM_SIZE in KB, divide by 4 and multiply by 1024.
byte_en_bram #(LINES, preload_file, USE_PRELOAD_FILE) inst_data_ram (
.clk(clk),
.addr_a(portA.addr[$clog2(LINES)- 1:0]),
.en_a(portA.en),
.be_a(portA.be),
.data_in_a(portA.data_in),
.data_out_a(portA.data_out),
.addr_b(portB.addr[$clog2(LINES)- 1:0]),
.en_b(portB.en),
.be_b(portB.be),
.data_in_b(portB.data_in),
.data_out_b(portB.data_out)
);
endmodule

34
local_memory/local_memory_interface.sv
View file

@ -1,34 +0,0 @@
/*
* Copyright © 2018 Eric Matthews, Lesley Shannon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Initial code developed under the supervision of Dr. Lesley Shannon,
* Reconfigurable Computing Lab, Simon Fraser University.
*
* Author(s):
* Eric Matthews <ematthew@sfu.ca>
*/
interface local_memory_interface;
logic[29:0] addr;
logic en;
logic[3:0] be;
logic[31:0] data_in;
logic[31:0] data_out;
modport slave (input addr, en, be, data_in, output data_out);
modport master (output addr, en, be, data_in, input data_out);
endinterface

267
scripts/xilinx/cva5_wrapper_IP.tcl
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@ -1,267 +0,0 @@
#*****************************************************************************************
# Vivado (TM) v2018.3 (64-bit)
#
# tmp_edit_project.tcl: Tcl script for re-creating project 'tmp_edit_project'
#
# Generated by Vivado on Thu Dec 20 14:43:20 PST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# Set the reference directory for source file relative paths (by default the value is script directory path)
#set origin_dir [ file dirname [ file normalize [ info script ] ] ]
set origin_dir [file dirname [info script]]
puts $origin_dir
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
# Set the project name
set _xil_proj_name_ "cva5_wrapper_IP"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
set _xil_proj_name_ $::user_project_name
}
variable script_file
set script_file "cva5_wrapper_IP.tcl"
# Help information for this script
proc print_help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--project_name <name>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--project_name <name>\] Create project with the specified name. Default"
puts " name is the name of the project from where this"
puts " script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < $::argc} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
"--help" { print_help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
#This is where the IP project gets stored ?
set orig_proj_dir "[file normalize "$origin_dir/"]"
# Create project
create_project ${_xil_proj_name_} $origin_dir/${_xil_proj_name_} -part xc7z020clg484-1
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Reconstruct message rules
# None
# Set project properties
set obj [current_project]
set_property -name "board_part" -value "digilentinc.com:zedboard:part0:1.0" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_language" -value "Verilog" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
#import all sources from cva5 repo directory
#Zavier: Eric says we only want the wrapper, and whatever type/interface file we need at first.
#The reasoning is: less files at initial package, less worry
#import_files -fileset [get_filesets sources_1] $origin_dir/core
#import_files -fileset [get_filesets sources_1] $origin_dir/l2_arbiter
#import_files -fileset [get_filesets sources_1] $origin_dir/local_memory
import_files -norecurse $origin_dir/../../core/common_components/vendor_support/xilinx/cva5_wrapper_xilinx.sv -force
import_files -norecurse $origin_dir/../../l2_arbiter/l2_external_interfaces.sv -force
import_files -norecurse $origin_dir/../../local_memory/local_memory_interface.sv -force
import_files -norecurse $origin_dir/../../core/types_and_interfaces/external_interfaces.sv -force
import_files -norecurse $origin_dir/../../core/types_and_interfaces/cva5_config.sv -force
import_files -norecurse $origin_dir/../../core/types_and_interfaces/riscv_types.sv -force
import_files -norecurse $origin_dir/../../core/types_and_interfaces/cva5_types.sv -force
import_files -norecurse $origin_dir/../../core/types_and_interfaces/csr_types.sv -force
import_files -norecurse $origin_dir/../../core/types_and_interfaces/fpu_types.sv -force
import_files -norecurse $origin_dir/../../l2_arbiter/l2_config_and_types.sv -force
# Set IP repository paths
set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/cva5_wrapper_IP"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
# Add/Import constrs file and set constrs file properties
#set file "[file normalize "$origin_dir/examples/zedboard/zedboard_master_XDC_RevC_D_v3.xdc"]"
#set file_imported [import_files -fileset constrs_1 [list $file]]
# Set 'sources_1' fileset file properties for remote files
# None
# Set 'sources_1' fileset file properties for local files
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "cva5_wrapper_xilinx" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_file" -value " ${origin_dir}/core/cva5_wrapper_xilinx.sv" -objects $obj
# Remove interface files for cva5
puts "INFO: Project created:${_xil_proj_name_}"
#Removal of SystemVerilog interface files, so initial IP packaging can be done
#CUrrently Vivado 2018.1 complains if there is any SV interfaces during the intial packaging
#But if we were to re-add the SV interface files back into the IP and repackage it, SV will not complain
#export_ip_user_files -of_objects [get_files $origin_dir/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/imports/core/interfaces.sv] -no_script -reset -force -quiet
#remove_files $origin_dir/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/imports/core/interfaces.sv
#export_ip_user_files -of_objects [get_files $origin_dir/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/imports/l2_arbiter/l2_interfaces.sv] -no_script -reset -force -quiet
#remove_files $origin_dir/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/imports/l2_arbiter/l2_interfaces.sv
############## Initial IP Packaging########################################
ipx::package_project -import_files -force -root_dir $proj_dir
update_compile_order -fileset sources_1
set_property core_revision 2 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
# To set the axi interface as aximm and port map all the signals over #
set_property abstraction_type_vlnv xilinx.com:interface:aximm_rtl:1.0 [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property bus_type_vlnv xilinx.com:interface:aximm:1.0 [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
ipx::remove_port_map arid [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
ipx::add_port_map WLAST [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_wlast [ipx::get_port_maps WLAST -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map BREADY [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_bready [ipx::get_port_maps BREADY -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map AWLEN [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_awlen [ipx::get_port_maps AWLEN -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map AWREADY [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_awready [ipx::get_port_maps AWREADY -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map ARBURST [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_arburst [ipx::get_port_maps ARBURST -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map RRESP [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_rresp [ipx::get_port_maps RRESP -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map RVALID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_rvalid [ipx::get_port_maps RVALID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map AWID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_awid [ipx::get_port_maps AWID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map RLAST [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_rlast [ipx::get_port_maps RLAST -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map ARID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_arid [ipx::get_port_maps ARID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map AWCACHE [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_awcache [ipx::get_port_maps AWCACHE -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map WREADY [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_wready [ipx::get_port_maps WREADY -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map WSTRB [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_wstrb [ipx::get_port_maps WSTRB -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map BRESP [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_bresp [ipx::get_port_maps BRESP -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map BID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_bid [ipx::get_port_maps BID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map ARLEN [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_arlen [ipx::get_port_maps ARLEN -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map RDATA [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_rdata [ipx::get_port_maps RDATA -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map BVALID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_bvalid [ipx::get_port_maps BVALID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map ARCACHE [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_arcache [ipx::get_port_maps ARCACHE -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map RREADY [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_rready [ipx::get_port_maps RREADY -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map AWVALID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_awvalid [ipx::get_port_maps AWVALID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map ARSIZE [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_arsize [ipx::get_port_maps ARSIZE -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map WDATA [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_wdata [ipx::get_port_maps WDATA -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map AWSIZE [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_awsize [ipx::get_port_maps AWSIZE -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map RID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_rid [ipx::get_port_maps RID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map ARADDR [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_araddr [ipx::get_port_maps ARADDR -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map AWADDR [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_awaddr [ipx::get_port_maps AWADDR -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map ARREADY [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_arready [ipx::get_port_maps ARREADY -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map WVALID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_wvalid [ipx::get_port_maps WVALID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map ARVALID [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_arvalid [ipx::get_port_maps ARVALID -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
ipx::add_port_map AWBURST [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
set_property physical_name m_axi_awburst [ipx::get_port_maps AWBURST -of_objects [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]]
#####Re-Adding of SV interfaces files
#set_property ip_repo_paths $origin_dir/${_xil_proj_name_} [current_project]
#current_project $_xil_proj_name_
#update_ip_catalog
#import_files -norecurse $origin_dir/l2_arbiter/l2_interfaces.sv -force
#import_files -norecurse $origin_dir/core/interfaces.sv -force
#####Re-Adding of project files
set_property ip_repo_paths $origin_dir/../../${_xil_proj_name_} [current_project]
current_project $_xil_proj_name_
update_ip_catalog
import_files -fileset [get_filesets sources_1] $origin_dir/../../core
import_files -fileset [get_filesets sources_1] $origin_dir/../../l2_arbiter
import_files -fileset [get_filesets sources_1] $origin_dir/../../local_memory
############## Re-packaging of core
update_compile_order -fileset sources_1
ipx::merge_project_changes files [ipx::current_core]
set_property core_revision 3 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
current_project cva5_wrapper_IP
set_property "ip_repo_paths" "[file normalize "$origin_dir/cva5_wrapper_IP"]" $obj
update_ip_catalog -rebuild

167
scripts/xilinx/local_memory_IP.tcl
View file

@ -1,167 +0,0 @@
#*****************************************************************************************
# Vivado (TM) v2018.3 (64-bit)
#
# tmp_edit_project.tcl: Tcl script for re-creating project 'tmp_edit_project'
#
# Generated by Vivado on Thu Dec 20 14:43:20 PST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir [ file dirname [ file normalize [ info script ] ] ]
#set origin_dir [file dirname [info script]]
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
# Set the project name
set _xil_proj_name_ "local_memory_IP"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
set _xil_proj_name_ $::user_project_name
}
variable script_file
set script_file "local_memory_IP.tcl"
# Help information for this script
proc print_help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--project_name <name>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--project_name <name>\] Create project with the specified name. Default"
puts " name is the name of the project from where this"
puts " script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < $::argc} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
"--help" { print_help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
#This is where the IP project gets stored ?
set orig_proj_dir "[file normalize "$origin_dir/"]"
# Create project
create_project ${_xil_proj_name_} $origin_dir/${_xil_proj_name_} -part xc7z020clg484-1
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Reconstruct message rules
# None
# Set project properties
set obj [current_project]
set_property -name "board_part" -value "digilentinc.com:zedboard:part0:1.0" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_language" -value "Verilog" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
#import all sources from cva5 repo directory
import_files -fileset [get_filesets sources_1] $origin_dir/../../local_memory
import_files -norecurse $origin_dir/../../core/byte_en_BRAM.sv -force
import_files -norecurse $origin_dir/../../core/xilinx/xilinx_byte_enable_ram.sv -force
import_files -norecurse $origin_dir/../../core/cva5_config.sv -force
import_files -norecurse $origin_dir/../../core/cva5_types.sv -force
import_files -norecurse $origin_dir/../../core/riscv_types.sv -force
import_files -norecurse $origin_dir/../../core/csr_types.sv -force
# Set IP repository paths
#set obj [get_filesets sources_1]
#set_property "ip_repo_paths" "[file normalize "$origin_dir/Clean_CVA5_IP"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
# Add/Import constrs file and set constrs file properties
# Set 'sources_1' fileset file properties for remote files
# None
# Set 'sources_1' fileset file properties for local files
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "local_mem" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_file" -value "${origin_dir}/local_memory/local_mem.sv" -objects $obj
# Remove interface files for cva5
puts "INFO: Project created:${_xil_proj_name_}"
##############IP Packaging########################################
ipx::package_project -import_files -force -root_dir $proj_dir
update_compile_order -fileset sources_1
set_property core_revision 2 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
set_property ip_repo_paths $origin_dir/${_xil_proj_name_} [current_project]
current_project $_xil_proj_name_
update_ip_catalog
update_compile_order -fileset sources_1
ipx::merge_project_changes files [ipx::current_core]
set_property core_revision 3 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
current_project local_memory_IP
update_ip_catalog -rebuild -repo_path $origin_dir/${_xil_proj_name_}

11
tools/compile_order
View file

@ -5,12 +5,6 @@ core/types_and_interfaces/cva5_types.sv
core/types_and_interfaces/fpu_types.sv
core/types_and_interfaces/opcodes.sv
l2_arbiter/l2_config_and_types.sv
l2_arbiter/l2_interfaces.sv
l2_arbiter/l2_external_interfaces.sv
local_memory/local_memory_interface.sv
local_memory/local_mem.sv
core/types_and_interfaces/internal_interfaces.sv
core/types_and_interfaces/external_interfaces.sv
@ -19,7 +13,6 @@ core/common_components/ram/lutram_1w_mr.sv
core/common_components/ram/sdp_ram.sv
core/common_components/ram/sdp_ram_padded.sv
core/common_components/ram/tdp_ram.sv
core/common_components/ram/dual_port_bram.sv
core/common_components/set_clr_reg_with_rst.sv
core/common_components/one_hot_to_integer.sv
core/common_components/one_hot_mux.sv
@ -31,10 +24,6 @@ core/common_components/round_robin.sv
core/common_components/toggle_memory.sv
core/common_components/toggle_memory_set.sv
core/common_components/vendor_support/intel/intel_byte_enable_ram.sv
core/common_components/vendor_support/xilinx/xilinx_byte_enable_ram.sv
core/common_components/byte_en_bram.sv
core/execution_units/csr_unit.sv
core/execution_units/gc_unit.sv