Commit graph

11 commits

Author SHA1 Message Date
mohammadshahidzade
101987c502
adding the marchid (#30) 2025-03-17 20:19:22 -07:00
mohammadshahidzade
4efa1e2d03
Os fixes6 (#29)
* Support for atomic extension A
* Support instruction fence extension Zifencei
* Update CSRs to Version 20240411 and include compliant support for Zihpm, Sstc, and Smstateen extensions
* Support address translation
* Fixes interrupts and exception handling
* Adds interrupt controllers
* Support coherent multicore systems through a new data cache and arbiter
* Multiple bugfixes
* Adds new scripts for example systems in Vivado and LiteX
* Removes legacy, unused, and broken scripts, examples, and files

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Co-authored-by: Chris Keilbart <keilbartchris@gmail.com>
Co-authored-by: msa417 <msa417@ensc-rcl-14.engineering.sfu.ca>
Co-authored-by: Rajnesh Joshi <rajnesh.joshi28@gmail.com>
Co-authored-by: Rajnesh Joshi <rajneshj@sfu.ca>
2025-03-11 16:06:16 -07:00
Chris Keilbart
98f8be7d1e Add FPU 2024-03-19 09:58:22 -07:00
Chris Keilbart
8a9d805a90 Linter fixes 2023-06-20 09:24:58 -07:00
Eric Matthews
8769842249 Add dcache cbo instruction support
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-05-02 14:58:26 -04:00
Eric Matthews
1d0ac14e70 Cleanup unit writeback group and ID assignment
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-04-28 19:51:18 -04:00
Eric Matthews
1085a86a04 Mul cleanup
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-04-28 19:47:16 -04:00
Eric Matthews
89810cec57 Decode/Issue cleanup
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-04-28 14:18:35 -04:00
Eric Matthews
17c45f0050 Consolidate BRAM implementations
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-04-17 13:15:24 -04:00
Eric Matthews
24baf185e7 Convert remaining inferred lutram memories to lutram modules
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-04-14 23:06:22 -04:00
Eric Matthews
6b80905045 Reorganize source files
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-04-14 20:21:05 -04:00