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4efa1e2d03
* Support for atomic extension A * Support instruction fence extension Zifencei * Update CSRs to Version 20240411 and include compliant support for Zihpm, Sstc, and Smstateen extensions * Support address translation * Fixes interrupts and exception handling * Adds interrupt controllers * Support coherent multicore systems through a new data cache and arbiter * Multiple bugfixes * Adds new scripts for example systems in Vivado and LiteX * Removes legacy, unused, and broken scripts, examples, and files --------- Co-authored-by: Chris Keilbart <keilbartchris@gmail.com> Co-authored-by: msa417 <msa417@ensc-rcl-14.engineering.sfu.ca> Co-authored-by: Rajnesh Joshi <rajnesh.joshi28@gmail.com> Co-authored-by: Rajnesh Joshi <rajneshj@sfu.ca>
47 lines
1.4 KiB
Systemverilog
47 lines
1.4 KiB
Systemverilog
/*
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* Copyright © 2017, 2018 Eric Matthews, Lesley Shannon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Eric Matthews <ematthew@sfu.ca>
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*/
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module cycler
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#(
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parameter C_WIDTH = 2
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)
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(
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input logic clk,
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input logic rst,
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input logic en,
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output logic [C_WIDTH - 1: 0] one_hot
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);
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generate if (C_WIDTH == 1) begin : gen_width_one
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assign one_hot = 1;
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end else begin : gen_width_two_plus
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always_ff @ (posedge clk) begin
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if (rst)
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one_hot <= 1;
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else if (en)
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one_hot <= {one_hot[C_WIDTH-2:0],one_hot[C_WIDTH-1]};//rotate left
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end
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end
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endgenerate
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endmodule
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