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* Support for atomic extension A * Support instruction fence extension Zifencei * Update CSRs to Version 20240411 and include compliant support for Zihpm, Sstc, and Smstateen extensions * Support address translation * Fixes interrupts and exception handling * Adds interrupt controllers * Support coherent multicore systems through a new data cache and arbiter * Multiple bugfixes * Adds new scripts for example systems in Vivado and LiteX * Removes legacy, unused, and broken scripts, examples, and files --------- Co-authored-by: Chris Keilbart <keilbartchris@gmail.com> Co-authored-by: msa417 <msa417@ensc-rcl-14.engineering.sfu.ca> Co-authored-by: Rajnesh Joshi <rajnesh.joshi28@gmail.com> Co-authored-by: Rajnesh Joshi <rajneshj@sfu.ca> |
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ram | ||
clz.sv | ||
cva5_fifo.sv | ||
cycler.sv | ||
lfsr.sv | ||
one_hot_to_integer.sv | ||
priority_encoder.sv | ||
round_robin.sv | ||
set_clr_reg_with_rst.sv | ||
toggle_memory.sv | ||
toggle_memory_set.sv |