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4efa1e2d03
* Support for atomic extension A * Support instruction fence extension Zifencei * Update CSRs to Version 20240411 and include compliant support for Zihpm, Sstc, and Smstateen extensions * Support address translation * Fixes interrupts and exception handling * Adds interrupt controllers * Support coherent multicore systems through a new data cache and arbiter * Multiple bugfixes * Adds new scripts for example systems in Vivado and LiteX * Removes legacy, unused, and broken scripts, examples, and files --------- Co-authored-by: Chris Keilbart <keilbartchris@gmail.com> Co-authored-by: msa417 <msa417@ensc-rcl-14.engineering.sfu.ca> Co-authored-by: Rajnesh Joshi <rajnesh.joshi28@gmail.com> Co-authored-by: Rajnesh Joshi <rajneshj@sfu.ca>
93 lines
3 KiB
Systemverilog
93 lines
3 KiB
Systemverilog
/*
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* Copyright © 2021 Eric Matthews
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Eric Matthews <ematthew@sfu.ca>
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*/
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//3-16 bit LFSRs with additional feedback to support full 2^N range
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module lfsr
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#(
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parameter int unsigned WIDTH = 3,
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parameter NEEDS_RESET = 1
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)
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(
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input logic clk,
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input logic rst,
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input logic en,
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output logic [WIDTH-1:0] value
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);
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typedef struct packed {
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int unsigned NUM;
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bit [3:0][31:0] INDICIES;
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} tap_t;
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//XNOR taps for LFSR from 3-16 bits wide (source: Xilinx xapp052)
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localparam tap_t LFSR_TAPS [17] = '{
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//Dummy entries for widths 0-2
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'{NUM : 1, INDICIES : '{0,0,0,0}},
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'{NUM : 1, INDICIES : '{0,0,0,0}},
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'{NUM : 1, INDICIES : '{0,0,0,0}},
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//Number of taps and indicies[3:0] for LFSRs width 3 to 16
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'{NUM : 2, INDICIES : '{0,0,1,2}}, //3
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'{NUM : 2, INDICIES : '{0,0,2,3}}, //4
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'{NUM : 2, INDICIES : '{0,0,2,4}},
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'{NUM : 2, INDICIES : '{0,0,4,5}},
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'{NUM : 2, INDICIES : '{0,0,5,6}},
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'{NUM : 4, INDICIES : '{3,4,5,7}}, //8
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'{NUM : 2, INDICIES : '{0,0,4,8}},
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'{NUM : 2, INDICIES : '{0,0,6,9}},
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'{NUM : 2, INDICIES : '{0,0,8,10}},
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'{NUM : 4, INDICIES : '{0,3,5,11}}, //12
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'{NUM : 4, INDICIES : '{0,2,3,12}},
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'{NUM : 4, INDICIES : '{0,2,4,13}},
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'{NUM : 2, INDICIES : '{0,0,13,14}}, //15
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'{NUM : 4, INDICIES : '{3,12,14,15}} //16
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};
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localparam tap_t TAPS = LFSR_TAPS[WIDTH];
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logic [TAPS.NUM-1:0] feedback_input;
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logic feedback;
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////////////////////////////////////////////////////
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//Implementation
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generate if (WIDTH <= 2) begin : gen_width_one_or_two
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assign feedback = ~value[WIDTH-1];
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end
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else begin : gen_width_three_plus
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for (genvar i = 0; i < TAPS.NUM; i++) begin : gen_taps
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assign feedback_input[i] = value[int'(TAPS.INDICIES[i])];
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end
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//XNOR of taps and range extension to include all ones
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assign feedback = (~^feedback_input) ^ |value[WIDTH-2:0];
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end
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endgenerate
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initial value = 0;
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always_ff @ (posedge clk) begin
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if (NEEDS_RESET & rst)
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value <= '0;
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else if (en) begin
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value <= value << 1;
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value[0] <= feedback;
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end
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end
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endmodule
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