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Added specific test target to Makefile
This commit is contained in:
Florian Zaruba
parent
9f2c0be6af
commit
0593615513
7 changed files with 101 additions and 18 deletions
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@ -6,7 +6,7 @@ testALU:
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stage: test
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script:
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- make build
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- vsim-10.5c alu_tb_optimized -c +UVM_TESTNAME=alu_test -coverage -do "coverage save -onexit alu.ucdb; run -a; exit"
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- make alu
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- vcover report alu.ucdb
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- vcover report -html alu.ucdb
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artifacts:
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20
Makefile
20
Makefile
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@ -5,14 +5,20 @@
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# compile everything in the following library
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library = work
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# Top level module to compile
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top_level = alu_tb
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top_level = ariane
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test_top_level = alu_tb
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tests = alu scoreboard
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# path to agents
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agents = tb/agents/fu_if/fu_if.sv tb/agents/fu_if/fu_if_agent_pkg.sv \
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include/ariane_pkg.svh tb/agents/scoreboard_if/scoreboard_if.sv tb/agents/scoreboard_if/scoreboard_if_agent_pkg.sv
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interfaces = include/debug_if.svh include/mem_if.svh
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# this list contains the standalone components
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src = alu.sv tb/sequences/alu_sequence_pkg.sv tb/env/alu_env_pkg.sv tb/test/alu_lib_pkg.sv tb/alu_tb.sv \
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issue_read_operands.sv decoder.sv
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tb/scoreboard_tb.sv \
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if_stage.sv compressed_decoder.sv fetch_fifo.sv commit_stage.sv prefetch_buffer.sv \
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scoreboard.sv issue_read_operands.sv decoder.sv id_stage.sv util/cluster_clock_gating.sv regfile.sv ex_stage.sv ariane.sv \
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tb/core_tb.sv
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# Search here for include files (e.g.: non-standalone components)
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incdir = ./includes
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@ -29,21 +35,26 @@ list_incdir = $(foreach dir, ${incdir}, +incdir+$(dir))
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# Build the TB and module using QuestaSim
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build:
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# Create the library
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# rm -rf ${library}
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vlib${questa_version} ${library}
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# Suppress message that always_latch may not be checked thoroughly bu Questa.
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# Compile agents
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vlog${questa_version} ${compile_flag} -incr ${agents} ${list_incdir} -suppress 2583
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# Compile interfaces
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vlog${questa_version} ${compile_flag} -incr ${interfaces} ${list_incdir} -suppress 2583
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# Compile source files
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vlog${questa_version} ${compile_flag} -incr ${src} ${list_incdir} -suppress 2583
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# Optimize top level
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vopt${questa_version} ${compile_flag} ${top_level} -o ${top_level}_optimized +acc -check_synthesis
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vopt${questa_version} ${compile_flag} ${test_top_level} -o ${test_top_level}_optimized +acc -check_synthesis
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# Run the specified test case
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sim:
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# vsim${questa_version} ${top_level}_optimized -c -do "run -a"
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vsim${questa_version} ${top_level}_optimized +UVM_TESTNAME=${test_case} -do "run -a"
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$(tests):
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# Optimize top level
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vopt${questa_version} ${compile_flag} $@_tb -o $@_optimized +acc -check_synthesis
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vsim${questa_version} -c +UVM_TESTNAME=$@_test -coverage -do "coverage save -onexit $@.ucdb; run -a; exit" $@_tb_optimized
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# User Verilator to lint the target
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lint:
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verilator ${src} --lint-only \
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@ -51,5 +62,6 @@ lint:
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clean:
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rm -rf work/
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.PHONY:
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build lint
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@ -31,8 +31,8 @@ interface mem_if
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// Memory interface configured as slave
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modport Slave
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(
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input address, data_wdata, data_req, data_we, data_be,
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output data_gnt, data_rvalid, data_rdata
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output address, data_wdata, data_req, data_we, data_be,
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input data_gnt, data_rvalid, data_rdata
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);
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endinterface
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`endif
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@ -29,19 +29,19 @@ interface scoreboard_if (input clk);
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scoreboard_entry issue_instr;
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wire issue_instr_valid;
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wire issue_ack;
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wire [63:0] pc;
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wire [4:0] trans_id;
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wire [63:0] wdata;
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wire wb_valid;
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// Scoreboard interface configured as master
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clocking mck @(posedge clk);
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default input #1 output #5; // save timing
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output flush, rs1_address, rs2_address, commit_ack, decoded_instr, decoded_instr_valid, issue_ack, pc, wdata, wb_valid;
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output flush, rs1_address, rs2_address, commit_ack, decoded_instr, decoded_instr_valid, issue_ack, trans_id, wdata, wb_valid;
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input full, rd_clobber, rs1, rs1_valid, rs2, rs2_valid, commit_instr, issue_instr, issue_instr_valid;
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endclocking
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// Scoreboard interface configured in passive mode (-> monitor)
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clocking pck @(posedge clk);
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input flush, rs1_address, rs2_address, commit_ack, decoded_instr, decoded_instr_valid, issue_ack, pc, wdata, wb_valid,
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input flush, rs1_address, rs2_address, commit_ack, decoded_instr, decoded_instr_valid, issue_ack, trans_id, wdata, wb_valid,
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full, rd_clobber, rs1, rs1_valid, rs2, rs2_valid, commit_instr, issue_instr, issue_instr_valid;
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endclocking
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71
tb/core_tb.sv
Executable file
71
tb/core_tb.sv
Executable file
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@ -0,0 +1,71 @@
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// Author: Florian Zaruba, ETH Zurich
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// Date: 15/04/2017
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// Description: Top level testbench module. Instantiates the top level DUT, configures
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// the virtual interfaces and starts the test passed by +UVM_TEST+
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//
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// Copyright (C) 2017 ETH Zurich, University of Bologna
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// All rights reserved.
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import ariane_pkg::*;
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module core_tb;
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logic clk_i;
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logic rst_ni;
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logic clock_en_i;
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logic test_en_i;
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logic fetch_enable_i;
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logic core_busy_o;
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logic [-1:0] ext_perf_counters_i;
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logic [63:0] boot_addr_i;
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logic [3:0] core_id_i;
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logic [5:0] cluster_id_i;
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mem_if instr_if();
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mem_if data_if();
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logic irq_i;
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logic [4:0] irq_id_i;
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logic irq_ack_o;
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logic irq_sec_i;
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logic sec_lvl_o;
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debug_if debug_if();
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ariane i_ariane (
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.clk_i (clk_i ),
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.rst_n (rst_ni ),
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.clock_en_i (clock_en_i ),
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.test_en_i (test_en_i ),
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.fetch_enable_i (fetch_enable_i ),
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.core_busy_o (core_busy_o ),
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.ext_perf_counters_i(ext_perf_counters_i),
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.boot_addr_i (boot_addr_i ),
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.core_id_i (core_id_i ),
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.cluster_id_i (cluster_id_i ),
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.instr_if (instr_if ),
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.data_if (data_if ),
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.irq_i (irq_i ),
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.irq_id_i (irq_id_i ),
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.irq_ack_o (irq_ack_o ),
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.irq_sec_i (irq_sec_i ),
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.sec_lvl_o (sec_lvl_o ),
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.debug_if (debug_if )
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);
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// clock process
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initial begin
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clk_i = 1'b0;
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rst_ni = 1'b0;
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repeat(8)
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#10ns clk_i = ~clk_i;
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rst_ni = 1'b1;
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forever
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#10ns clk_i = ~clk_i;
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end
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program testbench (mem_if instr_if);
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endprogram
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testbench tb(instr_if);
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endmodule
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@ -6,9 +6,9 @@ class Scoreboard;
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// utility function to get randomized input data
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static function automatic scoreboard_entry randomize_scoreboard();
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exception exception = { 64'h55, 63'h0, 1'b0};
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exception exception = { pc, 63'h0, 1'b0};
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scoreboard_entry entry = {
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pc, ALU, ADD, 5'h5, 5'h5, 5'h5, 64'h0, 1'b0, 1'b0, exception
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ALU, ADD, 5'h5, 5'h5, 5'h5, 64'h0, 1'b0, 1'b0, exception
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};
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pc++;
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return entry;
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@ -27,9 +27,9 @@ class Scoreboard;
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endfunction : get_issue
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// write back to scoreboard
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function void write_back(logic [63:0] pc, logic [63:0] value);
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function void write_back(logic [4:0] trans_id, logic [63:0] value);
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for (int i = 0; i < $size(issued_instructions); i++) begin
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if (issued_instructions[i].pc == pc) begin
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if (issued_instructions[i].trans_id == trans_id) begin
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issued_instructions[i].valid = 1'b1;
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issued_instructions[i].result = value;
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end
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@ -37,7 +37,7 @@ module scoreboard_tb;
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.issue_instr_o ( scoreboard_if.issue_instr ),
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.issue_instr_valid_o ( scoreboard_if.issue_instr_valid ),
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.issue_ack_i ( scoreboard_if.issue_ack ),
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.pc_i ( scoreboard_if.pc ),
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.trans_id_i ( scoreboard_if.trans_id ),
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.wdata_i ( scoreboard_if.wdata ),
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.wb_valid_i ( scoreboard_if.wb_valid )
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);
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@ -107,10 +107,10 @@ module scoreboard_tb;
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repeat ($urandom_range(1,20)) @(scoreboard_if.mck);
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wb_lock.get(1);
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// $display("Time: %t, Writing Back: %0h", $time, thread_copy.pc);
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scoreboard_if.mck.pc <= thread_copy.pc;
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scoreboard_if.mck.trans_id <= thread_copy.trans_id;
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scoreboard_if.mck.wdata <= rand_data;
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scoreboard_if.mck.wb_valid <= 1'b1;
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sb.write_back(thread_copy.pc, rand_data);
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sb.write_back(thread_copy.trans_id, rand_data);
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@(scoreboard_if.mck);
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scoreboard_if.mck.wb_valid <= 1'b0;
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wb_lock.put(1);
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@ -158,7 +158,7 @@ module scoreboard_tb;
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@(scoreboard_if.pck);
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if (scoreboard_if.pck.issue_instr_valid == 1'b1 && scoreboard_if.pck.issue_ack) begin
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tmp_sbe = sb.get_issue();
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assert (tmp_sbe.pc == issue_instruction.pc) else $error("Issue instruction mismatch. Expected: %0h Got: %0h", tmp_sbe, issue_instruction);
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assert (tmp_sbe.trans_id == issue_instruction.trans_id) else $error("Issue instruction mismatch. Expected: %0h Got: %0h", tmp_sbe, issue_instruction);
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end
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end
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end
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